c082b8981f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 52.200s | 2.709ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.120s | 37.772us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.220s | 33.619us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 20.260s | 4.613ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.080s | 1.514ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.700s | 200.940us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.220s | 33.619us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.080s | 1.514ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.740s | 13.055us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.350s | 128.912us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.423h | 578.867ms | 45 | 50 | 90.00 |
| V2 | burst_write | kmac_burst_write | 20.314m | 164.627ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 53.500m | 478.062ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 46.759m | 252.696ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 32.751m | 132.224ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 24.783m | 48.638ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 59.506m | 144.855ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 29.665m | 69.201ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 2.600s | 76.457us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 2.840s | 652.950us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.175m | 85.061ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.462m | 30.391ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 5.238m | 62.026ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.162m | 21.515ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 8.358m | 22.614ms | 48 | 50 | 96.00 |
| V2 | key_error | kmac_key_error | 11.740s | 15.002ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 45.030s | 2.275ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 39.710s | 3.689ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.308m | 15.334ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 51.780s | 2.054ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 1.107h | 163.103ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.830s | 29.339us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.880s | 87.034us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.430s | 330.925us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.430s | 330.925us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.120s | 37.772us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.220s | 33.619us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.080s | 1.514ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.510s | 1.003ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.120s | 37.772us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.220s | 33.619us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.080s | 1.514ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.510s | 1.003ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 681 | 690 | 98.70 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.570s | 57.477us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.570s | 57.477us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.570s | 57.477us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.570s | 57.477us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.020s | 420.143us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.246m | 40.552ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.220s | 1.159ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.220s | 1.159ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 51.780s | 2.054ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 52.200s | 2.709ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.175m | 85.061ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.570s | 57.477us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.246m | 40.552ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.246m | 40.552ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.246m | 40.552ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 52.200s | 2.709ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 51.780s | 2.054ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.246m | 40.552ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.136m | 142.292ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 52.200s | 2.709ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 2.370m | 4.949ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 871 | 890 | 97.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 21 | 84.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.66 | 95.77 | 90.51 | 100.00 | 66.94 | 93.67 | 98.84 | 95.86 |
UVM_ERROR (cip_base_vseq.sv:848) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
0.kmac_stress_all_with_rand_reset.73786684456524821474663676224341986425280042379393431310832805367778292378308
Line 388, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 741419759 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 741419759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.17489397585200921344526203427073073424369677936366446552026533442855842307004
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5829750838 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5829750838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
1.kmac_long_msg_and_output.18194967682144716752393199270975370366814751298510245649695569103216143379426
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
Job ID: smart:7f4bd519-f2ae-449c-a573-a656af4bf870
10.kmac_long_msg_and_output.99509742387271566770543881968510951286355543780067002772497480548675815375202
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest/run.log
Job ID: smart:421f9904-b4e6-4b8b-bad2-5341afbdcb78
... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
2.kmac_stress_all_with_rand_reset.85349173569630388396924731629226440191583960441720496383986939798584552225689
Line 322, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3670217374 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
UVM_INFO @ 3670217374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_stress_all_with_rand_reset.67847293410856710593426857436800297479136752436790482922570814455037570808524
Line 331, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 323235018 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
UVM_INFO @ 323235018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
15.kmac_error.114714431594517222290380911795039757501890478920117115306784732806855615762997
Line 876, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.kmac_error.6571992901134100121512428120619521436644637720617403521456075854196706519489
Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_entropy_refresh has 1 failures.
33.kmac_entropy_refresh.28080788590230563903702327519129696675187913550910159538254645442141391669090
Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 6173749764 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (90 [0x5a] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 6173749764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
36.kmac_app.36930735973805476515933806334012950008124949100768268042401518712261756397377
Line 553, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_app/latest/run.log
UVM_FATAL @ 2150081033 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (34 [0x22] vs 156 [0x9c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2150081033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---