KMAC/UNMASKED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.106m	13.790ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	49.375us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	41.558us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.810s	5.952ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.530s	139.948us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.870s	93.765us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	41.558us	20	20	100.00
		kmac_csr_aliasing	7.530s	139.948us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	13.338us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.360s	67.393us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.328h	228.353ms	46	50	92.00
V2	burst_write	kmac_burst_write	19.259m	34.111ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	55.950m	288.481ms	5	5	100.00
		kmac_test_vectors_sha3_256	50.252m	87.061ms	5	5	100.00
		kmac_test_vectors_sha3_384	34.103m	58.938ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.730s	770.669us	5	5	100.00
		kmac_test_vectors_shake_128	38.250m	20.759ms	5	5	100.00
		kmac_test_vectors_shake_256	54.158m	537.032ms	5	5	100.00
		kmac_test_vectors_kmac	2.760s	81.034us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.870s	108.676us	5	5	100.00
V2	sideload	kmac_sideload	8.740m	21.381ms	50	50	100.00
V2	app	kmac_app	6.535m	71.793ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.781m	22.584ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.446m	183.735ms	50	50	100.00
V2	error	kmac_error	8.525m	87.311ms	50	50	100.00
V2	key_error	kmac_key_error	11.380s	11.930ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.860s	2.424ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.480s	2.817ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.750s	5.644ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.091m	3.363ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.047h	125.922ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	15.774us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	21.712us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.720s	719.629us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.720s	719.629us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	49.375us	5	5	100.00
		kmac_csr_rw	1.200s	41.558us	20	20	100.00
		kmac_csr_aliasing	7.530s	139.948us	5	5	100.00
		kmac_same_csr_outstanding	3.220s	1.690ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	49.375us	5	5	100.00
		kmac_csr_rw	1.200s	41.558us	20	20	100.00
		kmac_csr_aliasing	7.530s	139.948us	5	5	100.00
		kmac_same_csr_outstanding	3.220s	1.690ms	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.400s	52.695us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.400s	52.695us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.400s	52.695us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.400s	52.695us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.970s	520.382us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.123m	5.014ms	5	5	100.00
		kmac_tl_intg_err	5.380s	944.458us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.380s	944.458us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.091m	3.363ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.106m	13.790ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.740m	21.381ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.400s	52.695us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.123m	5.014ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.123m	5.014ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.123m	5.014ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.106m	13.790ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.091m	3.363ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.123m	5.014ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.721m	27.637ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.106m	13.790ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.024m	2.387ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			874	890	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.13	95.89	92.27	100.00	67.77	94.11	98.84	96.01

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.8309605281480226423203079971018586743155734388595300366724374405559567035508
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108373601 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108373601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.20769812961156509520880545930145091659317794008577028677418608033383574367450
    Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 870506682 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 870506682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test kmac_long_msg_and_output has 4 failures.
  - 22.kmac_long_msg_and_output.92709729872373636258099668370997158689692131986243092400378693624511893922230
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:1bc2b1c8-5a8e-4357-bcd4-8c8f17fd5986
```
  - 24.kmac_long_msg_and_output.79777577303607857030102147745543139788951570385528061027943077707095615620952
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:5fd860a3-a1a7-4934-aca4-add42d2d99e4
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app has 1 failures.

11.kmac_app.102335881786635937789094222978875893262252368556675289534561811651959392194527
Line 771, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_app/latest/run.log

  UVM_FATAL @ 13321162119 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (228 [0xe4] vs 7 [0x7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13321162119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

14.kmac_stress_all.71522281281545915199257134433368168581089811054166350776977751434217971743350
Line 1065, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_FATAL @ 50344454878 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (48 [0x30] vs 160 [0xa0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 50344454878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_stress_all.17608543434729787086427729653076851143234761281312540177337260273217718867650
Line 501, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest/run.log

  UVM_FATAL @ 54059482549 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (73 [0x49] vs 117 [0x75]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 54059482549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.93196407530572165950418612718946609896842959654787318765975455548499304377332
    Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 338896377 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 338896377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.50806353920536072317508257770309247663896981781773078945325334045594957289678
    Line 569, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2386903038 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2386903038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```