76588857da| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.036m | 14.583ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.120s | 131.780us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.200s | 27.494us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 16.020s | 579.605us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.070s | 1.908ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.740s | 88.998us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.200s | 27.494us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.070s | 1.908ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.740s | 17.838us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.570s | 166.971us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.376h | 89.262ms | 46 | 50 | 92.00 |
| V2 | burst_write | kmac_burst_write | 20.879m | 40.934ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 55.432m | 193.305ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 43.883m | 57.699ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 36.044m | 180.318ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 22.046m | 67.480ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.102h | 430.853ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 55.541m | 354.269ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 2.720s | 119.229us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 2.770s | 107.832us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 7.686m | 19.125ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.355m | 32.124ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 5.092m | 13.672ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.601m | 22.408ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 7.583m | 75.473ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 10.710s | 7.723ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 35.920s | 1.678ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 1.006m | 2.778ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.073m | 14.060ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 45.400s | 1.045ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 55.384m | 243.526ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.880s | 91.482us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.910s | 45.822us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.540s | 154.897us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.540s | 154.897us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.120s | 131.780us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.200s | 27.494us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.070s | 1.908ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.820s | 636.596us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.120s | 131.780us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.200s | 27.494us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.070s | 1.908ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.820s | 636.596us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 684 | 690 | 99.13 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.500s | 86.565us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.500s | 86.565us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.500s | 86.565us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.500s | 86.565us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.180s | 508.669us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.232m | 11.220ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.710s | 3.677ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.710s | 3.677ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 45.400s | 1.045ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.036m | 14.583ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 7.686m | 19.125ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.500s | 86.565us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.232m | 11.220ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.232m | 11.220ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.232m | 11.220ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.036m | 14.583ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 45.400s | 1.045ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.232m | 11.220ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.495m | 46.908ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.036m | 14.583ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.672m | 5.324ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 874 | 890 | 98.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 22 | 88.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.95 | 95.77 | 90.51 | 100.00 | 68.60 | 93.67 | 98.84 | 96.29 |
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
0.kmac_stress_all_with_rand_reset.47711642945686809716220432374190110236997050948502117298521064535360823977890
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 312665082 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 312665082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.12784485366105230873370652542039792781074730468111776242106026206982901251250
Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 847298486 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 847298486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
1.kmac_long_msg_and_output.77630704868133924313140309434959997366078900123676331834947697288962410862408
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
Job ID: smart:2292a6c4-1841-4bad-ad22-e4ef067cb3ab
16.kmac_long_msg_and_output.6660673342387918566006842959875264378196694708913760873293140344361106663308
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest/run.log
Job ID: smart:94f04aa0-23b6-4d7d-bd46-8e6062a626ae
... and 2 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_stress_all has 1 failures.
11.kmac_stress_all.3131447111537379012681925138415837560824984797597362674899650888378937345179
Line 821, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest/run.log
UVM_FATAL @ 53178719944 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (130 [0x82] vs 113 [0x71]) Mismatch between unmasked_digest[1] and dpi_digest[1]
UVM_INFO @ 53178719944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
40.kmac_entropy_refresh.20278749814302981038415260905792172626049285024509292866241130654084709659159
Line 479, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 6616439694 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (143 [0x8f] vs 41 [0x29]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 6616439694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
3.kmac_stress_all_with_rand_reset.89038280056323898780079209542876570366273971761919399987486273177772158611486
Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4487864071 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 4487864071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---