LC_CTRL Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.230s	496.794us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	73.507us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	15.827us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.530s	255.661us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	32.719us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	54.278us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	15.827us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	32.719us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.950s	118.887us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.990s	348.069us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.030s	14.677us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.540s	608.522us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.760s	1.997ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_prog_failure	5.540s	608.522us	50	50	100.00
		lc_ctrl_errors	20.760s	1.997ms	50	50	100.00
		lc_ctrl_security_escalation	15.910s	766.837us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.845m	4.800ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.770s	1.284ms	20	20	100.00
		lc_ctrl_jtag_errors	2.084m	4.958ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	21.920s	957.040us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.890s	1.068ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.770s	1.284ms	20	20	100.00
		lc_ctrl_jtag_errors	2.084m	4.958ms	20	20	100.00
		lc_ctrl_jtag_access	31.490s	1.441ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.490s	11.899ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.670s	286.410us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.780s	100.267us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.420s	2.669ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	30.160s	1.401ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.430s	50.323us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.770s	141.057us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.560s	135.890us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.121m	3.099ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.540s	84.402us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.067m	81.346ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.340s	27.380us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.520s	488.967us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.520s	488.967us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	73.507us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.827us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	32.719us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	179.123us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	73.507us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.827us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	32.719us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	179.123us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
		lc_ctrl_tl_intg_err	4.360s	120.047us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.360s	120.047us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.990s	348.069us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.059m	752.426us	50	50	100.00
		lc_ctrl_sec_cm	1.193m	441.669us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.910s	766.837us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.950s	118.887us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.890s	1.068ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.360s	774.469us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.360s	774.469us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.970s	637.177us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.260s	658.212us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.260s	658.212us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	24.928m	52.008ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			985	1030	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.83	97.18	94.99	91.98	97.67	95.67	98.48	94.82

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 25 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.1798770295
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:67161e3d-2ac1-4ce6-841b-07ed9c59b0a9
```
  - 1.lc_ctrl_stress_all_with_rand_reset.973257377
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4c0a6fbd-3f33-45e5-b8b6-6e4665424cdb
```
  - ... and 23 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 8 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.1981184025
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1047a832-0ff6-4308-b423-529d4da2fdfe
```
  - 12.lc_ctrl_stress_all_with_rand_reset.89979881
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4981025b-ed64-4549-8b93-9bb6fc888ffd
```
  - ... and 6 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 6 failures:

Test lc_ctrl_stress_all_with_rand_reset has 6 failures.

22.lc_ctrl_stress_all_with_rand_reset.3618133958
Line 11275, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 13409158641 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xaf9e4400
  UVM_INFO @ 13409158641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.lc_ctrl_stress_all_with_rand_reset.1149229576
Line 3818, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9598243669 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x2682fec4
  UVM_INFO @ 9598243669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

19.lc_ctrl_stress_all_with_rand_reset.3582481395
Line 7621, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5779937524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 5779937524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.lc_ctrl_stress_all_with_rand_reset.2952800656
Line 8819, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21578629537 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 21578629537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.150506670
    Line 19815, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74209534747 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 74209534747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.lc_ctrl_stress_all_with_rand_reset.1591296278
    Line 42851, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.lc_ctrl_stress_all_with_rand_reset.2169839383
    Line 3225, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1107189899 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 479854881 [0x1c9a0121]) Regname: lc_ctrl_reg_block.transition_token_1 reset value: 0x0
  UVM_INFO @ 1107189899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_ctrl reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.lc_ctrl_stress_all_with_rand_reset.2157044056
    Line 12831, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56027970094 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.transition_ctrl reset value: 0x0
  UVM_INFO @ 56027970094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```