LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.830s	563.272us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset			0	5	0.00
V1	csr_rw	lc_ctrl_csr_rw			0	20	0.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash			0	5	0.00
V1	csr_aliasing	lc_ctrl_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
V1		TOTAL			50	105	47.62
V2	state_post_trans	lc_ctrl_state_post_trans	10.080s	76.171us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.230s	313.062us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	11.402us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.930s	737.556us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.560s	1.972ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_prog_failure	6.930s	737.556us	50	50	100.00
		lc_ctrl_errors	20.560s	1.972ms	50	50	100.00
		lc_ctrl_security_escalation	14.370s	1.481ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.981m	3.136ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.750s	945.079us	20	20	100.00
		lc_ctrl_jtag_errors	2.105m	20.815ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.690s	613.526us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.320s	2.787ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.750s	945.079us	20	20	100.00
		lc_ctrl_jtag_errors	2.105m	20.815ms	20	20	100.00
		lc_ctrl_jtag_access	21.340s	887.810us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.330s	1.365ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset			0	10	0.00
		lc_ctrl_jtag_csr_rw			0	10	0.00
		lc_ctrl_jtag_csr_bit_bash			0	10	0.00
		lc_ctrl_jtag_csr_aliasing			0	10	0.00
		lc_ctrl_jtag_same_csr_outstanding			0	10	0.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset			0	10	0.00
		lc_ctrl_jtag_alert_test			0	10	0.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.360s	5.276ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.630s	81.507us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.631m	39.314ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.470s	63.925us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2		TOTAL			588	700	84.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
		lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.230s	313.062us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.550s	1.288ms	50	50	100.00
		lc_ctrl_sec_cm	37.970s	974.225us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.370s	1.481ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.080s	76.171us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.320s	2.787ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.160s	2.102ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.160s	2.102ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.700s	1.601ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.930s	6.233ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.930s	6.233ms	50	50	100.00
V2S		TOTAL			155	175	88.57
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.372h	166.972ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			808	1030	78.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	1	16.67
V2	27	27	17	62.96
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	97.89	96.04	95.74	100.00	98.55	99.00	96.25

Failure Buckets

Job killed most likely because its dependent job failed. has 185 failures:
- Test lc_ctrl_jtag_csr_hw_reset has 10 failures.
  - 0.lc_ctrl_jtag_csr_hw_reset.59950131893996960550834594953929618958107291376385057826926874331731422412450
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest/run.log
  - 1.lc_ctrl_jtag_csr_hw_reset.71665484009519111443141920351106352160210744948714146892235891802414373692139
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest/run.log
  - ... and 8 more failures.
- Test lc_ctrl_jtag_csr_rw has 10 failures.
  - 0.lc_ctrl_jtag_csr_rw.98518700924974654842895376043551922290796990635693585195088653785336972281443
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest/run.log
  - 1.lc_ctrl_jtag_csr_rw.70405266890973732723765879182639851604874160311501257064264685519481086474084
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest/run.log
  - ... and 8 more failures.
- Test lc_ctrl_jtag_csr_bit_bash has 10 failures.
  - 0.lc_ctrl_jtag_csr_bit_bash.11790798586004204309723710269361334616648464497006063962088867470264027340822
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest/run.log
  - 1.lc_ctrl_jtag_csr_bit_bash.46212736739978258360534995246280299352697204893071371582353579968882089221009
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest/run.log
  - ... and 8 more failures.
- Test lc_ctrl_jtag_csr_aliasing has 10 failures.
  - 0.lc_ctrl_jtag_csr_aliasing.32254158528586972012543512837104780392976800164552334367435197844827012174822
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest/run.log
  - 1.lc_ctrl_jtag_csr_aliasing.59599475322237538145862530486048406445918199717888688697855929669484777239194
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest/run.log
  - ... and 8 more failures.
- Test lc_ctrl_jtag_same_csr_outstanding has 10 failures.
  - 0.lc_ctrl_jtag_same_csr_outstanding.82097568454420649448311910484692665683779386138009711991651324054468883908691
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest/run.log
  - 1.lc_ctrl_jtag_same_csr_outstanding.99501735868779096086795476734350169248142034193097422699454629457997971715534
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest/run.log
  - ... and 8 more failures.
- ... and 10 more tests.
UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.46842563088629384101204172303312533688150015636656311945162727977358982958913
    Line 23405, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83881305049 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 83881305049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.19243574069047951400829094040411449138405231693079814824726438702499852500433
    Line 30766, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25776450975 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25776450975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 15.lc_ctrl_stress_all_with_rand_reset.111712632309042538610545472400453571194964604461648768673582837660835896054631
    Line 47690, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 21.lc_ctrl_stress_all_with_rand_reset.87243826327277096069702164048947666867444902504237556750763015962776963599126
    Line 39724, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 20.lc_ctrl_stress_all_with_rand_reset.4855193982275829148112151744118429628987014072535495224501264675596152315182
    Line 40110, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38053317706 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 38053317706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.lc_ctrl_stress_all_with_rand_reset.17017585690238425690444566039845218045699431335774525753872518405995280872646
    Line 10838, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34254156228 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 34254156228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

Test lc_ctrl_stress_all has 2 failures.

17.lc_ctrl_stress_all.23806148830744594283779806264791884206699980052446005412639320734821081986733
Line 4297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 936983454 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 936983454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.lc_ctrl_stress_all.83825667723858359242776119532856365999172426631447003535607660431431946878713
Line 12741, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 69756563626 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 69756563626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:
- Test cover_reg_top has 1 failures.
  - cover_reg_top
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/build.log
UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.33456304311614797366745454240506791989139384639740606490140971342968729703516
    Line 47931, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36791338411 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 36791338411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.lc_ctrl_stress_all_with_rand_reset.107588570630004510456199209758808169229021721994049448076886413278201669652670
    Line 24909, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65502165867 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 65502165867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```