e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 9.170s | 131.850us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 50 | 105 | 47.62 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 10.910s | 88.863us | 50 | 50 | 100.00 |
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 20.590s | 312.057us | 10 | 10 | 100.00 |
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 1.000s | 13.036us | 10 | 10 | 100.00 |
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 4.780s | 219.874us | 50 | 50 | 100.00 |
| V2 | lc_state_failure | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| V2 | lc_errors | lc_ctrl_errors | 23.940s | 3.854ms | 50 | 50 | 100.00 |
| V2 | security_escalation | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_prog_failure | 4.780s | 219.874us | 50 | 50 | 100.00 | ||
| lc_ctrl_errors | 23.940s | 3.854ms | 50 | 50 | 100.00 | ||
| lc_ctrl_security_escalation | 13.810s | 587.549us | 50 | 50 | 100.00 | ||
| lc_ctrl_jtag_state_failure | 1.270m | 13.466ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 14.870s | 1.167ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 1.858m | 16.186ms | 20 | 20 | 100.00 | ||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 14.730s | 1.719ms | 20 | 20 | 100.00 |
| lc_ctrl_jtag_state_post_trans | 42.870s | 1.363ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 14.870s | 1.167ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 1.858m | 16.186ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_access | 23.660s | 1.033ms | 50 | 50 | 100.00 | ||
| lc_ctrl_jtag_regwen_during_op | 30.610s | 1.724ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_hw_reset | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_rw | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_bit_bash | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_aliasing | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_same_csr_outstanding | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_alert_test | 0 | 10 | 0.00 | ||||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 6.390s | 225.535us | 10 | 10 | 100.00 |
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.710s | 145.177us | 50 | 50 | 100.00 |
| V2 | stress_all | lc_ctrl_stress_all | 5.305m | 16.355ms | 50 | 50 | 100.00 |
| V2 | alert_test | lc_ctrl_alert_test | 1.630s | 86.064us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 590 | 700 | 84.29 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 |
| lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 20.590s | 312.057us | 10 | 10 | 100.00 |
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 39.150s | 531.083us | 50 | 50 | 100.00 |
| lc_ctrl_sec_cm | 38.760s | 1.165ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 13.810s | 587.549us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 10.910s | 88.863us | 50 | 50 | 100.00 |
| lc_ctrl_jtag_state_post_trans | 42.870s | 1.363ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 31.650s | 2.189ms | 50 | 50 | 100.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 31.650s | 2.189ms | 50 | 50 | 100.00 |
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 22.270s | 2.610ms | 50 | 50 | 100.00 |
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 15.230s | 721.604us | 50 | 50 | 100.00 |
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 15.230s | 721.604us | 50 | 50 | 100.00 |
| V2S | TOTAL | 155 | 175 | 88.57 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 32.110m | 77.977ms | 27 | 50 | 54.00 |
| V3 | TOTAL | 27 | 50 | 54.00 | |||
| TOTAL | 822 | 1030 | 79.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 1 | 16.67 |
| V2 | 27 | 27 | 18 | 66.67 |
| V2S | 5 | 5 | 4 | 80.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 185 failures:
0.lc_ctrl_jtag_csr_hw_reset.35131438059817446545122539719519392727363099878176404934499771596487510272639
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest/run.log
1.lc_ctrl_jtag_csr_hw_reset.39581654809308290511949877773296917876251808103505670407005456287076675575015
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest/run.log
... and 8 more failures.
0.lc_ctrl_jtag_csr_rw.109362606824022573642080761846147767897915470141220093473145730609417902455571
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest/run.log
1.lc_ctrl_jtag_csr_rw.45985165360626282853197515423357716063852916529171224829030170177767864928771
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest/run.log
... and 8 more failures.
0.lc_ctrl_jtag_csr_bit_bash.72435581914548976322007969267048499463403631493650072473056936891399669811361
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest/run.log
1.lc_ctrl_jtag_csr_bit_bash.70995164273691729827922696633471435538703978438268060374254119586165363134994
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest/run.log
... and 8 more failures.
0.lc_ctrl_jtag_csr_aliasing.5772020175275448111858560580121066759808447231016976216786362013830644462397
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest/run.log
1.lc_ctrl_jtag_csr_aliasing.87990011447308499056206868999497620321911883551899278531283567680172972408340
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest/run.log
... and 8 more failures.
0.lc_ctrl_jtag_same_csr_outstanding.6304818434240326179013252346165859147042883013656146368282260830594182142316
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest/run.log
1.lc_ctrl_jtag_same_csr_outstanding.72766137913195581583503308065048229210592440773132170766924344414331138129558
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest/run.log
... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
7.lc_ctrl_stress_all_with_rand_reset.108545027219799536167981317277202940909579492364466227978891784930445000730746
Line 5121, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 83941403462 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 83941403462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.lc_ctrl_stress_all_with_rand_reset.40629526436991823076276882388948477977249982878065706801164049232415895095833
Line 13902, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36341567799 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36341567799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 5 failures:
31.lc_ctrl_stress_all_with_rand_reset.45878344641749466073246591284593390192690378919262962942438051416354938272413
Line 7697, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21430940876 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
UVM_INFO @ 21430940876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.lc_ctrl_stress_all_with_rand_reset.61124388758653083281360953068964361816018682640263982871853933559719026217539
Line 18527, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 210098988381 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
UVM_INFO @ 210098988381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
16.lc_ctrl_stress_all_with_rand_reset.108643689201825565213905525540979945069758997403322371303242915410737683755525
Line 3709, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25563837315 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 25563837315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.lc_ctrl_stress_all_with_rand_reset.37056943769777380775169018764541775254269118907080812081242473889034889516050
Line 27502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 42563948996 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 42563948996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:
Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:
cov_report
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log
Job ID: smart:28d99ee1-30a2-40b5-9113-13a2976eae1b