LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.850s	202.719us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	18.969us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	15.566us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.890s	68.085us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.540s	138.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	25.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	15.566us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	138.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.190s	520.497us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.620s	383.604us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	19.118us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.390s	1.173ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.750s	673.289us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_prog_failure	5.390s	1.173ms	50	50	100.00
		lc_ctrl_errors	21.750s	673.289us	50	50	100.00
		lc_ctrl_security_escalation	16.450s	2.583ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.446m	11.002ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.020s	1.281ms	20	20	100.00
		lc_ctrl_jtag_errors	1.578m	14.573ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.720s	4.060ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.470s	1.893ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.020s	1.281ms	20	20	100.00
		lc_ctrl_jtag_errors	1.578m	14.573ms	20	20	100.00
		lc_ctrl_jtag_access	18.350s	757.242us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.150s	3.382ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.770s	1.202ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.760s	88.621us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.850s	5.478ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.100s	644.476us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.740s	65.449us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.030s	430.103us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.520s	828.274us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	47.740s	1.975ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.110s	14.737us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.606m	18.001ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	62.432us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.450s	113.060us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.450s	113.060us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	18.969us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.566us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	138.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	160.938us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	18.969us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.566us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	138.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	160.938us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
		lc_ctrl_tl_intg_err	4.480s	119.026us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.480s	119.026us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.620s	383.604us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.220s	733.471us	50	50	100.00
		lc_ctrl_sec_cm	39.860s	225.785us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.450s	2.583ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.190s	520.497us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.470s	1.893ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.580s	2.074ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.580s	2.074ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.650s	14.639ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.900s	3.090ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.900s	3.090ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	39.648m	51.795ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.99	97.82	96.30	95.74	95.35	98.10	99.00	96.61

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.69617107899432232715314002836332743048020407337298348427890396203720935948750
      Line 6008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14090135930 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14090135930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.34958592459360273508446487416331775680160097910143842952102315701010827956230
      Line 5582, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7549702786 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7549702786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.77220321466226515676517552713434320093530281617743920392157296539530035162488
      Line 1943, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3711476329 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3711476329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.80379490447412345692498677138652807794890739566754520262713638507134720703855
      Line 13588, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32377047770 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 32377047770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.51969372093554054677362252072791782381222689842807449600437233056463253796053
      Line 12920, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10732636649 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10732636649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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