LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.130s	632.936us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	78.025us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	16.486us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.450s	251.441us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.810s	243.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.370s	56.473us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	16.486us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	243.883us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.420s	124.643us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.440s	717.773us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	19.931us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.580s	1.024ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.730s	612.176us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_prog_failure	4.580s	1.024ms	50	50	100.00
		lc_ctrl_errors	23.730s	612.176us	50	50	100.00
		lc_ctrl_security_escalation	16.070s	4.564ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.471m	21.283ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.060s	1.879ms	20	20	100.00
		lc_ctrl_jtag_errors	1.664m	3.838ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.540s	689.819us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.600s	4.176ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.060s	1.879ms	20	20	100.00
		lc_ctrl_jtag_errors	1.664m	3.838ms	20	20	100.00
		lc_ctrl_jtag_access	26.310s	2.339ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.800s	2.479ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.480s	209.978us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.470s	86.918us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.960s	2.389ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.880s	1.676ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.530s	76.432us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.570s	2.250ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.690s	180.982us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.376m	7.502ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.430s	25.416us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.126m	50.455ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.810s	138.431us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.960s	527.001us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.960s	527.001us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	78.025us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	16.486us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	243.883us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	42.978us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	78.025us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	16.486us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	243.883us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	42.978us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
		lc_ctrl_tl_intg_err	4.590s	1.318ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.590s	1.318ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.440s	717.773us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.980s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	944.178us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.070s	4.564ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.420s	124.643us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.600s	4.176ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.690s	7.940ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.690s	7.940ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.150s	2.633ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.220s	2.099ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.220s	2.099ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.276h	158.138ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 18 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.24889337451838391584219032024938046638916438748770469377032510567124091017583
    Line 50235, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40379251021 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40379251021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.66186646931416777782873576331813592730653185028422607089856292183610779085389
    Line 24453, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28141994848 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28141994848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 15.lc_ctrl_stress_all_with_rand_reset.65023128735933224418138871251136751071724688918533828102679512469662195066857
    Line 33748, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19708709971 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 19708709971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.lc_ctrl_stress_all_with_rand_reset.51631526500376705379258226859184413363569233643812273942221614677876985647602
    Line 18387, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6311965910 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 6311965910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test lc_ctrl_stress_all has 1 failures.
  - 29.lc_ctrl_stress_all.18271674911733138830283613603728913615873507364694965843470945959169537441754
    Line 5290, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 52685191625 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 52685191625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.30102634960754976206723850967316483015951427699570414994295930572976693238760
    Line 25846, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 10.lc_ctrl_stress_all_with_rand_reset.31796313360579573601601252670412855730418769766078940149843730536675743117908
    Line 57884, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.84068165127430238878443777385947227769146409990613250896359597730982007115938
    Line 30757, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16465293561 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 16465293561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.96465854032558524961193183797829727691066757637583631358696492648293793943902
    Line 21058, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15990649212 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15990649212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:
- Test lc_ctrl has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log
```
  Job ID: smart:40b3808c-f52b-49b1-8908-b937cbc2cb06
```

Past Results

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Testplan Progress

Failure Buckets

Past Results

GitHub Revision: `8d1fda3660`