LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.770s	271.888us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset			0	5	0.00
V1	csr_rw	lc_ctrl_csr_rw			0	20	0.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash			0	5	0.00
V1	csr_aliasing	lc_ctrl_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
V1		TOTAL			50	105	47.62
V2	state_post_trans	lc_ctrl_state_post_trans	11.210s	81.215us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.320s	1.480ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	11.769us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.930s	652.129us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.560s	1.360ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_prog_failure	4.930s	652.129us	50	50	100.00
		lc_ctrl_errors	25.560s	1.360ms	50	50	100.00
		lc_ctrl_security_escalation	19.040s	3.828ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.746m	11.940ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.010s	11.418ms	20	20	100.00
		lc_ctrl_jtag_errors	1.843m	84.005ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.460s	2.170ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	40.930s	5.328ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.010s	11.418ms	20	20	100.00
		lc_ctrl_jtag_errors	1.843m	84.005ms	20	20	100.00
		lc_ctrl_jtag_access	24.840s	1.006ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.720s	4.272ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset			0	10	0.00
		lc_ctrl_jtag_csr_rw			0	10	0.00
		lc_ctrl_jtag_csr_bit_bash			0	10	0.00
		lc_ctrl_jtag_csr_aliasing			0	10	0.00
		lc_ctrl_jtag_same_csr_outstanding			0	10	0.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset			0	10	0.00
		lc_ctrl_jtag_alert_test			0	10	0.00
V2	jtag_priority	lc_ctrl_jtag_priority	27.230s	1.129ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.640s	88.419us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.916m	87.727ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.620s	308.107us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2		TOTAL			590	700	84.29
V2S	tl_intg_err	lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
		lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.320s	1.480ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.540s	390.044us	50	50	100.00
		lc_ctrl_sec_cm	43.270s	512.890us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.040s	3.828ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.210s	81.215us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	40.930s	5.328ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.220s	965.407us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.220s	965.407us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.910s	2.372ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.490s	2.260ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.490s	2.260ms	50	50	100.00
V2S		TOTAL			155	175	88.57
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.454m	40.463ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			814	1030	79.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	1	16.67
V2	27	27	18	66.67
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.79	95.35	95.73	97.62	98.34	98.76	96.61

Failure Buckets

• Job killed most likely because its dependent job failed. has 185 failures:

  • Test lc_ctrl_jtag_csr_hw_reset has 10 failures.

    • 0.lc_ctrl_jtag_csr_hw_reset.106536149728334599683206451099335864910366020214414105275069331154334835662301
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest/run.log

    • 1.lc_ctrl_jtag_csr_hw_reset.62119755530045669354077520014730577256102873021970974338926116484817889877451
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_rw has 10 failures.

    • 0.lc_ctrl_jtag_csr_rw.8817773171391159395103775980016503431258394933588113751291257023075737578070
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest/run.log

    • 1.lc_ctrl_jtag_csr_rw.53190024189299623220617778723595373454341525173785925269262776139896799788400
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_bit_bash has 10 failures.

    • 0.lc_ctrl_jtag_csr_bit_bash.56909164269595605426639831070569537881925926987511882741055140864228975558605
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest/run.log

    • 1.lc_ctrl_jtag_csr_bit_bash.86178193946199473117632809866597280086841690509898266727424341781400427988795
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_aliasing has 10 failures.

    • 0.lc_ctrl_jtag_csr_aliasing.4553290122617016264238070648589310496161869873614464140673633781702322391494
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest/run.log

    • 1.lc_ctrl_jtag_csr_aliasing.11004070095360985754689886717948918950329700529259219048506398083141636571214
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_same_csr_outstanding has 10 failures.

    • 0.lc_ctrl_jtag_same_csr_outstanding.115165867069280454502898529621108350714499540300586593848216663848244032224613
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest/run.log

    • 1.lc_ctrl_jtag_same_csr_outstanding.4197284255648846039861325130285726014921463116244020506636411395286503682281
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest/run.log

    • ... and 8 more failures.

  • ... and 10 more tests.

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.98679663806230279147165756007180857252437864444793386777483749616164524564065
      Line 24655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 81648571176 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 81648571176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.97221424852897709132670399304599681502716620446151556086418910725146973890255
      Line 1012, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2405508745 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2405508745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.3010568994658304410730066730870112111413953310292235030765251918324866774018
      Line 25771, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29023085169 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 29023085169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.20120508300478186735444238299819723466893510085376347342002230161421206928210
      Line 18028, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9675421208 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 9675421208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:

  • Test cover_reg_top has 1 failures.
    • cover_reg_top
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/build.log

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.16334394578168992882454650108394392872143472013710875360291074128450449679799
      Line 30189, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42127843037 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 42127843037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.08_05.13.38
• 2024.03.08_05.12.44
• 2024.03.06_08.15.26
• 2024.03.06_08.14.16
• 2024.03.04_05.00.38
• 2024.03.04_04.59.27