bc285b7382
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
V1 | csr_rw | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
V1 | csr_aliasing | lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
V1 | TOTAL | 0 | 105 | 0.00 | |||
V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
lc_ctrl_errors | 0 | 50 | 0.00 | ||||
lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_hw_reset | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_rw | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_bit_bash | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_aliasing | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_same_csr_outstanding | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_alert_test | 0 | 10 | 0.00 | ||||
V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | TOTAL | 0 | 700 | 0.00 | |||
V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
V2S | TOTAL | 0 | 175 | 0.00 | |||
V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 0 | 1030 | 0.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 0 | 0.00 |
V2 | 27 | 27 | 0 | 0.00 |
V2S | 5 | 5 | 0 | 0.00 |
V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed.
has 1032 failures:
0.lc_ctrl_smoke.99971583577606776119623749791499841970807659461138507541469792144352994962522
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.105232132537427286574557678706967464175342795354843815137928330946953788319044
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.81346180838164541226383316842978721223231563420923284775000052484151644468802
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.32780201364818937281970461487613045918224379910768431030578197523382781964146
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.35025026816079536532310009466659035880150875107699871919341658173087989895139
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.83079337398244088460072684266598814433517994073654156154571440850871593101501
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.104321766601125978159987921908961975069054016025109982377221302997783054454160
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.88247015593450199845475625485500811681343423625129876042539696490077116099110
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.110176259835892313031739545619860506261064942418848055059004292809081463553356
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.66183846738382019385850842442338693846866990069412741120509423317519219249403
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan1_cluster:smart-5c798316-3a57-4e6a-b626-eee01e86ff59/output.tar.gz... / [* files][ * B/ * MiB] Tracker file doesn't match for download of /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/default/output.tar.gz. Restarting download from scratch. OSError: No such file or directory. -
has 1 failures:
Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan1_cluster:smart-b9eb62a9-*-49f8-a210-f7c52f885fc1/output.tar.gz... / [* files][ * B/ * MiB] Tracker file doesn't match for download of /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/output.tar.gz. Restarting download from scratch. OSError: No such file or directory. -
has 1 failures: