LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.230s	90.848us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	53.896us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	68.876us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.130s	332.890us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.460s	18.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.440s	475.769us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	68.876us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	18.792us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.830s	1.419ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.250s	1.014ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	39.443us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.880s	587.479us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.050s	1.122ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_prog_failure	6.880s	587.479us	50	50	100.00
		lc_ctrl_errors	24.050s	1.122ms	49	50	98.00
		lc_ctrl_security_escalation	16.930s	898.912us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.276m	4.149ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.780s	1.141ms	20	20	100.00
		lc_ctrl_jtag_errors	2.204m	22.233ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.660s	580.091us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.800s	982.574us	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.780s	1.141ms	20	20	100.00
		lc_ctrl_jtag_errors	2.204m	22.233ms	20	20	100.00
		lc_ctrl_jtag_access	19.670s	3.905ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.200s	5.385ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.970s	176.637us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.000s	299.858us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.570s	4.951ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.430s	7.592ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.980s	45.784us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.080s	174.029us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.250s	141.870us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	34.390s	1.458ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	17.479us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.344m	82.420ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.440s	33.738us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.450s	535.555us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.450s	535.555us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	53.896us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	68.876us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	18.792us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.460s	48.131us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	53.896us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	68.876us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	18.792us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.460s	48.131us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
		lc_ctrl_tl_intg_err	4.660s	961.418us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.660s	961.418us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.250s	1.014ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.240s	692.663us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	531.189us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.930s	898.912us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.830s	1.419ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.800s	982.574us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.330s	2.108ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.330s	2.108ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.810s	4.334ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.620s	5.755ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.620s	5.755ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.175h	47.243ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.9575075402154675246304902284230413706988161402452921924223263406756077150168
      Line 22964, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60290039474 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 60290039474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.103438994642612373279669852587716018544839113376740070783581436380825546626393
      Line 40855, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 150608358781 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 150608358781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.25035978462866103288325049903961601423255041882087833113125890192107177930574
      Line 18708, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11306988726 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11306988726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.6438639564359785609873708671710244399273883448183180867562387834273761233302
      Line 25124, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 114568225540 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 114568225540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 1.lc_ctrl_errors.48303927200844325960131149641947865499497591638518401536580889842542691024488
      Line 1171, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  60233005 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  60233005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.41938996258057720567637612452263638948216819076929832408880158371097357489300
      Line 43349, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:

  • Test lc_ctrl has 1 failures.
    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

Past Results

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