e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.280s | 20.305us | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 1.190s | 18.330us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 2.050s | 182.084us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.780s | 76.921us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 2.100s | 108.894us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.190s | 18.330us | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 1.780s | 76.921us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 105 | 52.38 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
| V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
| V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
| lc_ctrl_errors | 0 | 50 | 0.00 | ||||
| lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_hw_reset | 2.750s | 80.219us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 2.580s | 155.818us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 52.250s | 49.219ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 21.740s | 981.919us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 2.180s | 399.360us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 4.820s | 611.474us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_alert_test | 2.160s | 454.950us | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
| V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 5.330s | 130.646us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 5.330s | 130.646us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.280s | 20.305us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.190s | 18.330us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.780s | 76.921us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.090s | 50.652us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.280s | 20.305us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.190s | 18.330us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.780s | 76.921us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.090s | 50.652us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 110 | 700 | 15.71 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| lc_ctrl_tl_intg_err | 6.540s | 236.852us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 6.540s | 236.852us | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 175 | 11.43 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 185 | 1030 | 17.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 27 | 27 | 9 | 33.33 |
| V2S | 5 | 5 | 1 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.27 | 97.89 | 95.95 | 95.74 | 97.67 | 98.55 | 99.00 | 96.07 |
Job killed most likely because its dependent job failed. has 845 failures:
0.lc_ctrl_smoke.62757911033011871139490639944585167534459037098250291963609295218726425698895
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.50241775737059372723299958213182499771735029489004931173485729477867880207015
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.47556376031432751634377175460584070679539643411759256465390799400210917249600
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.58672662861975267286626741767570937164063035428719477662674881391755146616037
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.6004889221472191545630760512625478976623110705883710609272960591400428809230
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.32278479899376843011526660194638544055597334850691964974932347803524110045722
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.83225614688799850070290405232729626424105790535452907367656158936208952253876
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.57393764289499263110227481383552613753547225765367293068715461033293579745616
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.1487045378882855800289234425172775094127814435615913844166400527393912742416
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.54655285629610548431334435759944984625047268660960259445222305222679733859833
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/default/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures: