c187a82ee8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.070s | 18.298us | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 1.130s | 32.918us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 1.630s | 29.487us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.760s | 155.925us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 2.280s | 27.197us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.130s | 32.918us | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 1.760s | 155.925us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 105 | 52.38 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
| V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
| V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
| lc_ctrl_errors | 0 | 50 | 0.00 | ||||
| lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_hw_reset | 5.130s | 840.402us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 2.150s | 258.748us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 37.060s | 7.262ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 13.450s | 1.125ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 1.950s | 43.524us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 4.670s | 852.485us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_alert_test | 2.270s | 447.302us | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
| V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 3.400s | 49.085us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 3.400s | 49.085us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.070s | 18.298us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.130s | 32.918us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.760s | 155.925us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 1.910s | 79.757us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.070s | 18.298us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.130s | 32.918us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.760s | 155.925us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 1.910s | 79.757us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 110 | 700 | 15.71 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| lc_ctrl_tl_intg_err | 4.510s | 498.475us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 4.510s | 498.475us | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 175 | 11.43 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 185 | 1030 | 17.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 27 | 27 | 9 | 33.33 |
| V2S | 5 | 5 | 1 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.94 | 97.82 | 96.21 | 93.31 | 97.62 | 98.52 | 99.00 | 96.07 |
Job killed most likely because its dependent job failed. has 845 failures:
0.lc_ctrl_smoke.54305194571337756173369525278822561808233076069968737175577678750851749494134
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.17177567307917999534468995506561238660443930201255463180907052343363904505765
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.91775711587463115274487895262902011222337674403578994218048136954124635996756
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.93444635312814149914132730929885273076273217599685838018749094194037575283716
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.17145752257053539053398033660874067358967240469347423810380427330219849986647
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.61842358222647795008017640467431666063730588279355466394138841079051339117730
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.39109969917250747457018022771036450628337573370682620098654927005799393139026
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.15998253005344923112488599784462655908916622983467540363219518394151796224622
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.66812770996001218103946666019444944575239737284321381931883264132499355160254
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.95920901864816085535885564648032881665793914417222108405479349213446895821521
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/default/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures: