LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	16.940s	3.311ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	195.689us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.280s	16.945us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.310s	356.343us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	60.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	26.213us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.280s	16.945us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	60.531us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.550s	64.632us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.160s	400.988us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	14.130us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.070s	112.497us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.400s	2.345ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_prog_failure	5.070s	112.497us	50	50	100.00
		lc_ctrl_errors	27.400s	2.345ms	50	50	100.00
		lc_ctrl_security_escalation	14.690s	1.961ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.466m	2.615ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.890s	2.858ms	20	20	100.00
		lc_ctrl_jtag_errors	1.471m	3.233ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.390s	2.826ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.840s	1.308ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.890s	2.858ms	20	20	100.00
		lc_ctrl_jtag_errors	1.471m	3.233ms	20	20	100.00
		lc_ctrl_jtag_access	29.180s	4.618ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.280s	1.407ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.320s	158.501us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.860s	158.122us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.620s	9.464ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.540s	3.516ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	154.500us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.210s	1.192ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.550s	320.759us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.570s	501.834us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.080s	11.440us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	17.880m	139.739ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.350s	22.518us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.970s	675.343us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.970s	675.343us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	195.689us	5	5	100.00
		lc_ctrl_csr_rw	1.280s	16.945us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	60.531us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	183.509us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	195.689us	5	5	100.00
		lc_ctrl_csr_rw	1.280s	16.945us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	60.531us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	183.509us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
		lc_ctrl_tl_intg_err	4.490s	120.785us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.490s	120.785us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.160s	400.988us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.140s	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	229.396us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.690s	1.961ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.550s	64.632us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.840s	1.308ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.810s	4.091ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.810s	4.091ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.100s	622.174us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.460s	462.093us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.460s	462.093us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	49.040m	196.645ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.52386154947406110929964540696994860476473083943161844534822990301898420391552
      Line 17196, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66644897268 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 66644897268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.55529001082702265152101336683757624817767074524946794101787932915884636937469
      Line 10077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19093547447 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19093547447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.47659521481902821815172966130038264469778527380042404828419880156600697216297
      Line 2913, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2504754009 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2504754009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.75305797698297219196113548681915790949001048670289004351113512015793141446203
      Line 1287, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 949138297 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 949138297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 10.lc_ctrl_stress_all.109583044329139163430072964551008579838977900203191307144717791705022672287182
      Line 6030, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8135361146 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8135361146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.94464094289419596761382958179818529846309054739266813983087761641356651277984
      Line 12946, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15785574347 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 15785574347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:c700dd5f-d103-4fef-97bc-7a264a58a860
      

Past Results

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