LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.290s	245.791us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	17.006us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	34.965us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.910s	175.469us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.780s	146.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.690s	34.884us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	34.965us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	146.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.970s	124.269us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.500s	1.556ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.427us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.370s	82.454us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.750s	555.472us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_prog_failure	4.370s	82.454us	50	50	100.00
		lc_ctrl_errors	23.750s	555.472us	49	50	98.00
		lc_ctrl_security_escalation	15.300s	1.608ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.996m	71.442ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.040s	1.622ms	20	20	100.00
		lc_ctrl_jtag_errors	1.674m	14.648ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.530s	390.441us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.310s	3.883ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.040s	1.622ms	20	20	100.00
		lc_ctrl_jtag_errors	1.674m	14.648ms	20	20	100.00
		lc_ctrl_jtag_access	20.410s	875.308us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.950s	1.404ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.430s	106.422us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.050s	554.039us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.560s	3.730ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.770s	643.718us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.490s	77.706us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.720s	274.383us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.780s	1.881ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.460s	10.006ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.400s	19.373us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	5.680m	13.062ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.340s	29.089us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.360s	314.418us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.360s	314.418us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	17.006us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	34.965us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	146.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	45.019us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	17.006us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	34.965us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	146.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	45.019us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
		lc_ctrl_tl_intg_err	7.160s	1.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	7.160s	1.099ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.500s	1.556ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.250s	742.299us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	265.973us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.300s	1.608ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.970s	124.269us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.310s	3.883ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.770s	1.377ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.770s	1.377ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.450s	778.904us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.510s	747.474us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.510s	747.474us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.562h	213.788ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.252768522611048422918735878448975166838436982061110839230462087102472455085
      Line 5942, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5831993536 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5831993536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.72899281095825849160343825628873571925447352289041077432327820402303627465350
      Line 35980, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48685183924 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 48685183924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.11358275746084249766093747937203618926451272076108222946837959225704166760460
      Line 40242, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 27.lc_ctrl_stress_all_with_rand_reset.44074536253030752667092375477919761134217705467865749409626692379094612369491
      Line 78158, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 3.lc_ctrl_errors.39541443167371142493422286312123293652485118938662445047220775549203920075915
      Line 2523, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 630441413 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 630441413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 7.lc_ctrl_jtag_priority.20582081459016888886574269317783011440272214397006704975446341555491029041900
      Line 558, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10006133507 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10006133507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan2_cluster:smart-fcae42c5-*-4cb4-*-b4244d85178b/output.tar.gz... OSError: No such file or directory. / [* files][ * B/ * MiB] has 1 failures:

  • Test lc_ctrl has 1 failures.
    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

Past Results

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• 2024.03.18_04.37.37
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