LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.150s	205.397us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	14.795us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	13.423us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.010s	203.764us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.860s	40.342us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.860s	372.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	13.423us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.342us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.670s	63.990us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	29.650s	441.403us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	13.108us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.860s	427.607us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.740s	1.033ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_prog_failure	4.860s	427.607us	50	50	100.00
		lc_ctrl_errors	26.740s	1.033ms	50	50	100.00
		lc_ctrl_security_escalation	20.490s	578.451us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.271m	15.914ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.440s	1.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.703m	7.239ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.800s	1.189ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.020s	4.371ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.440s	1.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.703m	7.239ms	20	20	100.00
		lc_ctrl_jtag_access	22.660s	1.881ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.860s	2.606ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.400s	311.893us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.860s	279.665us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	19.960s	2.404ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.110s	7.188ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	135.268us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.200s	785.293us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.470s	170.416us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.540s	706.976us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	14.923us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.326m	18.468ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.480s	61.237us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.880s	133.387us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.880s	133.387us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	14.795us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	13.423us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.342us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	179.027us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	14.795us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	13.423us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.342us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	179.027us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
		lc_ctrl_tl_intg_err	15.200s	3.732ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	15.200s	3.732ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	29.650s	441.403us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.190s	4.442ms	50	50	100.00
		lc_ctrl_sec_cm	37.200s	2.238ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.490s	578.451us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.670s	63.990us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.020s	4.371ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.700s	1.658ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.700s	1.658ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.140s	12.611ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.970s	489.196us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.970s	489.196us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.907h	338.753ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	97.82	96.21	93.31	100.00	98.52	98.76	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.90314718643871003951631098374280746128117903338502239293082080042878366657582
      Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1620146585 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1620146585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.37394995520025217033885757258037709572881288254250066733999467302769874961752
      Line 5218, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11899099197 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11899099197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.15069974737330863768962880992934050193219265473703749353636808815789761481166
      Line 42409, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 47.lc_ctrl_stress_all_with_rand_reset.84770929941033845413228436011695879318118224784387596825673949362188784054477
      Line 38901, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.10080939835379838066742760238245753454847074209660379311184971794198248983301
      Line 51262, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 231966756213 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 231966756213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.113062433896715660320047453326341571640152998683708994023286822796153879715095
      Line 4979, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12296916547 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 12296916547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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