LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.800s	3.029ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	15.692us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	15.058us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.130s	351.678us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.600s	119.317us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.830s	22.351us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	15.058us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	119.317us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.060s	413.198us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.340s	1.181ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	14.022us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.380s	1.100ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.720s	573.947us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_prog_failure	6.380s	1.100ms	50	50	100.00
		lc_ctrl_errors	22.720s	573.947us	50	50	100.00
		lc_ctrl_security_escalation	16.880s	1.628ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.194m	4.187ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.410s	1.386ms	20	20	100.00
		lc_ctrl_jtag_errors	1.955m	4.549ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.110s	2.706ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.900s	3.132ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.410s	1.386ms	20	20	100.00
		lc_ctrl_jtag_errors	1.955m	4.549ms	20	20	100.00
		lc_ctrl_jtag_access	20.060s	1.565ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.450s	3.031ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.060s	108.172us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.490s	132.190us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	32.270s	2.813ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.390s	3.326ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	36.032us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.430s	930.226us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.340s	140.677us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.722m	9.200ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	76.269us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.868m	18.157ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.450s	60.241us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.360s	412.647us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.360s	412.647us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	15.692us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.058us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	119.317us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	88.856us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	15.692us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.058us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	119.317us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	88.856us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
		lc_ctrl_tl_intg_err	4.220s	420.926us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.220s	420.926us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.340s	1.181ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.950s	2.164ms	50	50	100.00
		lc_ctrl_sec_cm	43.930s	860.544us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.880s	1.628ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.060s	413.198us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.900s	3.132ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.050s	2.009ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.050s	2.009ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.480s	1.828ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.450s	1.838ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.450s	1.838ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.461h	156.673ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.33045570743012579969135866695455460218883578420488261688318708867950324940370
      Line 27594, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14841936979 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14841936979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.67409479292865533491851250290999354931272768484328608431700263133213338276813
      Line 18016, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9807958853 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9807958853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.65668646791316983407871103636314328705171214941483862273622929966205730480304
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:dd384335-d738-4f0a-a40e-8f941f382256
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.52776112032794220858494365957730862945596642551723832270278258834847609853455
      Line 9263, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71232318168 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 71232318168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:8b265faa-d1d6-4113-bd7c-8d3578bd242f
      

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