LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.870s	807.568us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	20.147us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	57.432us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.440s	130.818us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.670s	151.758us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.000s	201.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	57.432us	20	20	100.00
		lc_ctrl_csr_aliasing	1.670s	151.758us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.770s	424.513us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.970s	1.251ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.997us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.680s	520.292us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.190s	2.426ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_prog_failure	5.680s	520.292us	50	50	100.00
		lc_ctrl_errors	26.190s	2.426ms	50	50	100.00
		lc_ctrl_security_escalation	14.300s	1.349ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.920m	4.330ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.040s	3.294ms	20	20	100.00
		lc_ctrl_jtag_errors	1.906m	4.418ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.800s	7.778ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.620s	711.758us	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.040s	3.294ms	20	20	100.00
		lc_ctrl_jtag_errors	1.906m	4.418ms	20	20	100.00
		lc_ctrl_jtag_access	22.330s	6.670ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.680s	1.317ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.610s	235.235us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.190s	607.227us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.320s	4.137ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.770s	576.352us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.450s	191.036us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.100s	567.976us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.860s	55.915us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	20.780s	3.623ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.670s	23.954us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.005m	34.310ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.360s	27.952us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.450s	301.345us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.450s	301.345us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	20.147us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	57.432us	20	20	100.00
		lc_ctrl_csr_aliasing	1.670s	151.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	76.663us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	20.147us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	57.432us	20	20	100.00
		lc_ctrl_csr_aliasing	1.670s	151.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	76.663us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
		lc_ctrl_tl_intg_err	4.780s	542.028us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.780s	542.028us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.970s	1.251ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	43.890s	1.876ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	424.651us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.300s	1.349ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.770s	424.513us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.620s	711.758us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.080s	626.084us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.080s	626.084us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.590s	1.204ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.570s	3.843ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.570s	3.843ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	21.344m	41.426ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.19276235819875712550173146096633765907436502261320812910684735273954868889599
      Line 21729, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69530845227 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 69530845227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.13402213163759091158797920763816717088022627411552573703087827570292386940103
      Line 25556, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34820389580 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34820389580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.59778972297940768287837659122685217272291061735432747538514258628779314669802
      Line 30069, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10550315897 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10550315897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.26483792212889290208050971469657873099158015751790695484133396628347182668429
      Line 32138, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 151551457238 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 151551457238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.86302146566046897694473825579348724624631572594936586533094329643788249646735
      Line 14909, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25465799154 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 25465799154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 40.lc_ctrl_stress_all.20457892071137460781713225041347920325013547471381968190939161662329611629265
      Line 4330, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/40.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 377712988 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 377712988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:fed454f9-2793-445b-9696-061c8cc69e0e
      

Past Results

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• 2024.03.27_04.40.56
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