LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.320s	317.468us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	55.720us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	29.564us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.990s	543.478us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.780s	148.507us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.820s	36.879us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	29.564us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	148.507us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.460s	390.751us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.240s	702.646us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	14.031us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.410s	182.634us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.740s	495.097us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_prog_failure	4.410s	182.634us	50	50	100.00
		lc_ctrl_errors	20.740s	495.097us	50	50	100.00
		lc_ctrl_security_escalation	16.530s	6.100ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.664m	3.323ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.790s	2.758ms	20	20	100.00
		lc_ctrl_jtag_errors	1.286m	2.664ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.530s	776.837us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.580s	1.312ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.790s	2.758ms	20	20	100.00
		lc_ctrl_jtag_errors	1.286m	2.664ms	20	20	100.00
		lc_ctrl_jtag_access	21.630s	921.214us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.730s	5.499ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.970s	1.773ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.940s	823.546us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.680s	5.066ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.990s	786.120us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	59.851us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.410s	844.193us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.930s	99.840us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.860s	11.960ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.130s	14.472us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.321m	468.815ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	31.488us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.790s	165.439us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.790s	165.439us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	55.720us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	29.564us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	148.507us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.170s	101.400us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	55.720us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	29.564us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	148.507us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.170s	101.400us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
		lc_ctrl_tl_intg_err	7.100s	4.481ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	7.100s	4.481ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.240s	702.646us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.200s	390.444us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	1.080ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.530s	6.100ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.460s	390.751us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.580s	1.312ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.970s	6.586ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.970s	6.586ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.190s	2.023ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.800s	1.580ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.800s	1.580ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.760h	26.545ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	97.79	95.89	93.30	100.00	98.34	99.00	96.79

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.34302638119000530728168556425973563301372015071502021735853623639193794121078
      Line 14459, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33967026812 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 33967026812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.41495693066251357066982419734714168318529730610266422480126490513554390598815
      Line 49395, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30585315433 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30585315433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.5454128678784526796827479331023311435105476635218311069549475392430108978534
      Line 7357, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16432188140 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 16432188140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.93847664104996093687313381737388163345712760027993673046853159246009527230273
      Line 12946, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12197053705 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 12197053705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.2526983804821630656290044373797763173253737609560819189147054456346304674268
      Line 32702, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 44.lc_ctrl_stress_all_with_rand_reset.84770243530131720460556189171933411145574200952289587708154988633671180104215
      Line 46971, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 3.lc_ctrl_jtag_priority.45757829158295544491294605880590839359539500238138653200946702291451048743492
      Line 683, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10005196484 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10005196484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.104854295662936024322783826914557103024095849730725964090604576839675234676302
      Line 556, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 331822031 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 331822031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.40605394680933415682671759638172622065128941063818042506281479811360885694080
      Line 22755, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 144605094415 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 144605094415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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