LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.520s	879.578us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	200.081us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	72.989us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.910s	81.844us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	329.016us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.320s	458.836us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	72.989us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	329.016us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.640s	127.899us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.610s	424.628us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	87.974us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.090s	414.410us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.390s	1.211ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_prog_failure	5.090s	414.410us	50	50	100.00
		lc_ctrl_errors	23.390s	1.211ms	50	50	100.00
		lc_ctrl_security_escalation	16.630s	924.614us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.571m	12.465ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.960s	806.761us	20	20	100.00
		lc_ctrl_jtag_errors	2.000m	17.481ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.020s	16.042ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.530s	558.859us	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.960s	806.761us	20	20	100.00
		lc_ctrl_jtag_errors	2.000m	17.481ms	19	20	95.00
		lc_ctrl_jtag_access	29.330s	5.019ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.790s	4.664ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.410s	632.068us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.010s	205.224us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.040s	952.429us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.820s	572.757us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.100s	199.556us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.340s	761.145us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.390s	76.896us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.280s	2.949ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.390s	39.543us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.211m	26.982ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	28.103us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.310s	386.957us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.310s	386.957us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	200.081us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	72.989us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	329.016us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.570s	50.362us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	200.081us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	72.989us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	329.016us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.570s	50.362us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.670s	569.630us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.670s	569.630us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.610s	424.628us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.770s	617.512us	50	50	100.00
		lc_ctrl_sec_cm	39.060s	1.025ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.630s	924.614us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.640s	127.899us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.530s	558.859us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.220s	3.193ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.220s	3.193ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.020s	2.332ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.100s	2.653ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.100s	2.653ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.064h	207.562ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.79	95.80	93.30	100.00	98.13	99.00	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.14210859423966004538285249050322352724832983695029870574247452925689853342260
      Line 47715, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 170974389678 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 170974389678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.20832259578843518971332025620988971135403597533868543685249882279340451168117
      Line 25834, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51109750833 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 51109750833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.31517843265953337713585177149772057186978078957912086563095088364029292842819
      Line 19692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11884068239 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 11884068239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.5463044943785344213473377077011494180000180540034845482794104134580717990016
      Line 36591, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72222237668 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 72222237668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.50484343982038355340263650075865902993170545370624189275706067871323486508856
      Line 45424, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 33.lc_ctrl_stress_all_with_rand_reset.30907801320476015592389273241187799448224368001182915143852105341961138326802
      Line 40883, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.6842944069603772340567976168372760798262001465191758213475307822851691832123
      Line 35495, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17862631485 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17862631485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.lc_ctrl_stress_all_with_rand_reset.12084618618239005826766411264459358017820832342171949543007515775154238643730
      Line 14819, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19747235846 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 19747235846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 0.lc_ctrl_jtag_errors.105782067467278634021671038682403426167041205558661190497039983786643709740915
      Line 591, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 816021731 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 816021731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.03.22_04.37.54
• 2024.03.22_04.36.47
• 2024.03.20_03.41.04
• 2024.03.20_03.39.59
• 2024.03.18_04.37.37
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