LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.020s	303.823us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.270s	17.537us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.190us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.130s	125.586us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	34.257us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.680s	44.273us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.190us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	34.257us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.900s	142.950us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.690s	406.664us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	20.942us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.050s	115.051us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.920s	946.416us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_prog_failure	5.050s	115.051us	50	50	100.00
		lc_ctrl_errors	28.920s	946.416us	50	50	100.00
		lc_ctrl_security_escalation	17.010s	6.545ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.264m	7.705ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.310s	724.781us	20	20	100.00
		lc_ctrl_jtag_errors	1.329m	5.717ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.940s	2.079ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.780s	1.069ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.310s	724.781us	20	20	100.00
		lc_ctrl_jtag_errors	1.329m	5.717ms	20	20	100.00
		lc_ctrl_jtag_access	26.900s	1.162ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.570s	4.708ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.100s	246.378us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.620s	168.187us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.860s	2.685ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.960s	1.140ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	38.808us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.610s	116.141us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.360s	262.637us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	30.530s	3.538ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.600s	72.007us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.144m	17.310ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.370s	52.177us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.890s	1.190ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.890s	1.190ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.270s	17.537us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.190us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	34.257us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	67.152us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.270s	17.537us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.190us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	34.257us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	67.152us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	232.483us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	232.483us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.690s	406.664us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.010s	2.793ms	50	50	100.00
		lc_ctrl_sec_cm	40.780s	984.997us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.010s	6.545ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.900s	142.950us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.780s	1.069ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.240s	4.341ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.240s	4.341ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.780s	3.337ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.660s	754.944us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.660s	754.944us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.058h	201.516ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	97.89	96.31	93.31	100.00	98.55	99.00	96.79

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.29969863485893281070058659397770433485335526855547314147048850096141187401306
      Line 45670, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51562678495 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 51562678495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.30882597454909445658194857875019250752448174088876303797777752560204663708634
      Line 8282, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12519414204 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12519414204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.13658389467716165316708912007878060169469661585457198233147450157838148551330
      Line 6901, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6611572719 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6611572719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.33189968895658715402248106859902207107939737857117870329962319461439395733219
      Line 42022, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68533110544 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 68533110544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 48.lc_ctrl_stress_all.73316357772656014460026819094391193716738554907239273716247585473835428383779
      Line 10088, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 17159380077 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17159380077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.7111484081105710904752005943568335968643338210785107878309021155793278419684
      Line 30867, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 28.lc_ctrl_stress_all_with_rand_reset.85105513092599722826720180216698290353932001368676232211861384974429618224910
      Line 53014, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.113762893723799368341172938709416188820475914460620086463998861832948839439200
      Line 34030, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46144549815 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 46144549815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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