LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.870s	94.583us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	224.921us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	19.027us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.870s	177.145us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	94.360us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.880s	93.930us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	19.027us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	94.360us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.890s	214.526us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	11.100s	2.679ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.910s	21.558us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.170s	164.623us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.050s	5.436ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_prog_failure	7.170s	164.623us	50	50	100.00
		lc_ctrl_errors	18.050s	5.436ms	50	50	100.00
		lc_ctrl_security_escalation	15.660s	439.848us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.626m	5.947ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.780s	1.026ms	20	20	100.00
		lc_ctrl_jtag_errors	1.611m	13.301ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.890s	530.214us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.250s	7.225ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.780s	1.026ms	20	20	100.00
		lc_ctrl_jtag_errors	1.611m	13.301ms	20	20	100.00
		lc_ctrl_jtag_access	15.850s	1.778ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.690s	5.607ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.380s	121.658us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.600s	980.117us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.460s	5.910ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.380s	3.327ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	173.935us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.480s	176.379us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.600s	44.016us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	39.680s	24.116ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	23.350us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.504m	66.303ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.400s	64.870us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.540s	621.706us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.540s	621.706us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	224.921us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.027us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	94.360us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	174.937us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	224.921us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.027us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	94.360us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	174.937us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
		lc_ctrl_tl_intg_err	3.820s	746.290us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.820s	746.290us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	11.100s	2.679ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.980s	709.640us	50	50	100.00
		lc_ctrl_sec_cm	40.090s	791.732us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.660s	439.848us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.890s	214.526us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.250s	7.225ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.410s	813.889us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.410s	813.889us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.650s	1.857ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.520s	15.189ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.520s	15.189ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	25.569m	30.601ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.22384692076930799278719766509977618407463234630122888163813780755836865566787
      Line 15056, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16842332000 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16842332000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.16956071000056501681945851389826435908885674375344300959434021677398553642454
      Line 21247, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57008454325 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 57008454325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.5667482279163649206513649776484756994431808611930836591127186856760444110235
      Line 14306, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36141855619 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 36141855619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.lc_ctrl_stress_all_with_rand_reset.88877941346730534524369155149240410407578228924285526670035381938076185325047
      Line 10301, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 85928693177 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 85928693177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.44893244879285663602990673304550813327427583819646971463942312310897477726474
      Line 18490, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57804631842 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 57804631842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.44856937339567862368127941531054870405159335230116808005680174023449538025213
      Line 19285, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41751336128 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 41751336128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.49278904459846005059031407748275572523257074523617852241761365705248099686156
      Line 28481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_merge/merged.vdb/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:

  • Test lc_ctrl has 1 failures.
    • cov_merge
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test lc_ctrl has 1 failures.
    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

Past Results

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