LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.220s	220.486us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	18.216us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	23.294us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.090s	173.934us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.350s	20.547us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.120s	197.129us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	23.294us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	20.547us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.110s	317.456us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.680s	1.385ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	39.120us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.760s	264.033us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.950s	3.296ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_prog_failure	4.760s	264.033us	50	50	100.00
		lc_ctrl_errors	22.950s	3.296ms	50	50	100.00
		lc_ctrl_security_escalation	15.680s	804.729us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.416m	2.468ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.130s	1.004ms	20	20	100.00
		lc_ctrl_jtag_errors	1.729m	3.727ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.470s	555.649us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.320s	723.992us	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.130s	1.004ms	20	20	100.00
		lc_ctrl_jtag_errors	1.729m	3.727ms	20	20	100.00
		lc_ctrl_jtag_access	24.960s	15.103ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.700s	1.584ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.740s	134.422us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.140s	115.851us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	55.140s	3.727ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.950s	2.282ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.190s	54.928us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.680s	300.107us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.820s	514.313us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.610s	17.118ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	15.075us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.745m	24.318ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.440s	31.836us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.110s	271.502us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.110s	271.502us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	18.216us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	23.294us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	20.547us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	280.802us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	18.216us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	23.294us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	20.547us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	280.802us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
		lc_ctrl_tl_intg_err	4.380s	123.998us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.380s	123.998us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.680s	1.385ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.410s	1.618ms	50	50	100.00
		lc_ctrl_sec_cm	25.570s	640.126us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.680s	804.729us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.110s	317.456us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.320s	723.992us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.570s	1.497ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.570s	1.497ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.380s	4.205ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.250s	508.648us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.250s	508.648us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.015h	136.969ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.82	96.21	93.31	97.67	98.10	98.76	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.56448130345282332815218776656566543841570405221550045354070564548115216822647
      Line 18652, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66947591922 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 66947591922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.84795863771109494122548214754804865488260796398349996827482140241606149283543
      Line 5755, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5486781907 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5486781907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.44487484544603885549976910195301810003244108647182503842096964496905487748757
      Line 1598, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 631637999 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 631637999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 49.lc_ctrl_stress_all.60356360325068583186171949150748351574537167276181006634633880163065468015882
      Line 2234, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5931604299 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5931604299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.39863501788407295667399400256267851695246122703442961168862988038723209102822
      Line 11506, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63576450178 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 63576450178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.lc_ctrl_stress_all_with_rand_reset.99915399261278353999274827106109584144192738095435575779164372858802441059640
      Line 28615, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18850142977 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 18850142977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.28731843760024853527169118664982731902727726467371929008610683111087608026442
      Line 29442, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• lint
• 2024.04.01_04.38.01
• 2024.03.29_04.07.56
• 2024.03.29_04.06.47
• 2024.03.27_04.40.56
• 2024.03.27_04.40.02
• 2024.03.25_03.59.47