LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.580s	111.748us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	74.692us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	15.687us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.250s	242.657us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.340s	100.732us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.650s	60.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	15.687us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	100.732us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.370s	334.416us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.070s	358.256us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	12.421us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.150s	554.748us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.590s	881.770us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_prog_failure	4.150s	554.748us	50	50	100.00
		lc_ctrl_errors	27.590s	881.770us	50	50	100.00
		lc_ctrl_security_escalation	14.840s	1.521ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.585m	3.353ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	3.217ms	20	20	100.00
		lc_ctrl_jtag_errors	2.432m	5.322ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.940s	824.221us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.730s	1.058ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	3.217ms	20	20	100.00
		lc_ctrl_jtag_errors	2.432m	5.322ms	20	20	100.00
		lc_ctrl_jtag_access	26.150s	4.619ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.410s	6.038ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.870s	250.939us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.090s	109.305us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.920s	1.614ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.200s	782.990us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.910s	45.130us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.880s	1.224ms	10	10	100.00
		lc_ctrl_jtag_alert_test	1.910s	317.143us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.840s	4.931ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	36.382us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.493m	20.535ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.240s	22.413us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.740s	396.262us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.740s	396.262us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	74.692us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.687us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	100.732us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	141.700us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	74.692us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.687us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	100.732us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	141.700us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.850s	109.543us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.850s	109.543us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.070s	358.256us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.790s	4.935ms	50	50	100.00
		lc_ctrl_sec_cm	36.370s	1.345ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.840s	1.521ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.370s	334.416us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.730s	1.058ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.270s	9.037ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.270s	9.037ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.400s	3.274ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.960s	2.231ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.960s	2.231ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	22.320m	43.361ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.17434576869986914327580744201186440452696984384223419600094746332437858995196
      Line 21073, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28070909937 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28070909937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.110171354105104588868112330953896887412072234513952609231193306700228945595081
      Line 20951, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13130327425 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13130327425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 9.lc_ctrl_stress_all.101452725359909595034157790005312370169004239407157156365732423221011034356811
      Line 5600, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9662503218 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 9662503218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.994965177004220017332092713953086951733829196067675144838876818329294633587
      Line 26431, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29633982885 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 29633982885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:4f0c4f7c-2856-449d-8fcc-c51052be8bd5
      

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