1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.150s | 51.556us | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 1.160s | 16.083us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 3.100s | 97.076us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.700s | 43.348us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 2.190s | 60.240us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.160s | 16.083us | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 1.700s | 43.348us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 105 | 52.38 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
| V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
| V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
| lc_ctrl_errors | 0 | 50 | 0.00 | ||||
| lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_hw_reset | 4.010s | 589.609us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 1.950s | 147.972us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 28.610s | 2.651ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 26.420s | 2.450ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 1.810s | 137.779us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 6.490s | 278.971us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_alert_test | 2.900s | 208.755us | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
| V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 5.930s | 556.809us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 5.930s | 556.809us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.150s | 51.556us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.160s | 16.083us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.700s | 43.348us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.070s | 91.385us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.150s | 51.556us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.160s | 16.083us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.700s | 43.348us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.070s | 91.385us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 110 | 700 | 15.71 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| lc_ctrl_tl_intg_err | 4.040s | 112.672us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 4.040s | 112.672us | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 175 | 11.43 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 185 | 1030 | 17.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 27 | 27 | 9 | 33.33 |
| V2S | 5 | 5 | 1 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.27 | 97.89 | 96.22 | 93.31 | 100.00 | 98.55 | 98.51 | 96.43 |
Job killed most likely because its dependent job failed. has 845 failures:
0.lc_ctrl_smoke.107219886885799943576459956262287437496498920296259959755302162307196554968207
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.49701296795465730458840476671995107648011839870880054356785986716305662117987
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.32300596288430692813830599326910211606289031155298735771774261098591656226106
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.47706987143527490395518819276820375373089851029633242343229872885263201174159
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.54738396916955924902077978201082243890241358635465125851820808396473550315177
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.53482885830129938738854983702532517339566965975083153677441744926672620933685
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.26240613195711311967719123264869134337470630647045952521142704083837547661720
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.72958989344515615762542942982802623879025702211079695542249578739514004686023
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.109110769735668751806863014684543036181761536005574933961478465858779923798803
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.53570709352805636612405595554808881053011836383015612662324921676258261390059
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/default/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures: