LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.890s	239.526us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	17.653us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.881us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.200s	102.963us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	37.471us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.930s	62.790us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.881us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	37.471us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.020s	307.042us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.710s	362.147us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	10.787us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.280s	1.138ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.450s	3.472ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_prog_failure	6.280s	1.138ms	50	50	100.00
		lc_ctrl_errors	19.450s	3.472ms	50	50	100.00
		lc_ctrl_security_escalation	17.690s	535.593us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.145m	15.901ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	871.445us	20	20	100.00
		lc_ctrl_jtag_errors	2.442m	5.718ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.790s	392.047us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.320s	880.779us	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	871.445us	20	20	100.00
		lc_ctrl_jtag_errors	2.442m	5.718ms	20	20	100.00
		lc_ctrl_jtag_access	25.490s	6.714ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.060s	1.388ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.160s	441.980us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.470s	248.510us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.360s	6.957ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.250s	5.996ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.910s	44.146us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.910s	883.714us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.090s	245.783us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.760s	3.479ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	19.366us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.858m	70.905ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.520s	29.317us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.760s	470.182us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.760s	470.182us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	17.653us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.881us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	37.471us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	43.785us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	17.653us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.881us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	37.471us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	43.785us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.250s	3.733ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.250s	3.733ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.710s	362.147us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.960s	347.423us	50	50	100.00
		lc_ctrl_sec_cm	35.870s	2.058ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.690s	535.593us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.020s	307.042us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.320s	880.779us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.540s	1.053ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.540s	1.053ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.400s	590.786us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.850s	3.523ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.850s	3.523ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	28.885m	409.243ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.82	96.03	93.31	97.62	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.85867593570457387212895818808547792054726585644078738935072177681896463723408
      Line 40104, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 198763265425 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 198763265425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.54888250182450076945628438278296002242795661121304980033987047043224920414630
      Line 10051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17547500953 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17547500953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.33585349549185170288214831259641592641481312578499456137127215807951026110030
      Line 6917, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1564934130 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1564934130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.84834614595348335719010642235150541245094971394551412131285675160698474160992
      Line 16925, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37839848321 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 37839848321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 25.lc_ctrl_stress_all.106343751286367030409437434039062774567188363076616782201962707993372913894421
      Line 14805, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9053066582 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 9053066582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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