LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.300s	310.451us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	67.687us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	54.571us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.950s	28.884us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.800s	36.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.980s	24.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	54.571us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	36.558us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.530s	556.888us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.650s	430.149us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	10.954us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.700s	156.512us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.630s	2.719ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_prog_failure	6.700s	156.512us	50	50	100.00
		lc_ctrl_errors	24.630s	2.719ms	50	50	100.00
		lc_ctrl_security_escalation	13.700s	3.217ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.517m	10.171ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.590s	14.899ms	20	20	100.00
		lc_ctrl_jtag_errors	1.198m	2.756ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.490s	2.443ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.060s	4.654ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.590s	14.899ms	20	20	100.00
		lc_ctrl_jtag_errors	1.198m	2.756ms	20	20	100.00
		lc_ctrl_jtag_access	27.330s	6.640ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.930s	1.315ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.820s	4.672ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.090s	62.156us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.930s	2.545ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.150s	3.663ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	42.549us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.790s	242.687us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.920s	110.776us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.430s	1.076ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.500s	92.923us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.005m	18.247ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.390s	70.707us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.160s	542.433us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.160s	542.433us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	67.687us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	54.571us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	36.558us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	473.194us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	67.687us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	54.571us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	36.558us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	473.194us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
		lc_ctrl_tl_intg_err	3.630s	80.642us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.630s	80.642us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.650s	430.149us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.180s	752.088us	50	50	100.00
		lc_ctrl_sec_cm	39.800s	435.345us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	13.700s	3.217ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.530s	556.888us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.060s	4.654ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.340s	813.499us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.340s	813.499us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.070s	3.974ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.310s	669.068us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.310s	669.068us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	43.815m	272.587ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.89	95.95	93.31	97.67	98.55	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.30540210452116386991798284116938001168687352353084542506062525353570481153405
      Line 7809, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34621178095 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34621178095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.105612379780654189069374998688658729519737129007543248282546910822475219865057
      Line 26875, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13466813340 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13466813340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 47.lc_ctrl_stress_all_with_rand_reset.61686294462479637180431523800522616330090701269791283314683784736966816159272
      Line 17082, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8825157872 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 8825157872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.lc_ctrl_stress_all_with_rand_reset.71188513965673086798479271158562771209355919821698201549065460191114920509554
      Line 17986, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 86254058420 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 86254058420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.106218343448090421052477138375862885717997401255217428936157224285673943232988
      Line 47282, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.3907220912040852285884936860693480835225030761638618540092958069184018718327
      Line 9120, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17595343903 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17595343903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.51366795721614702113556919936028762432163533652181648263384599195575444867365
      Line 49908, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 177465274099 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 177465274099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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