e3fb01b5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 8.000s | 36.765us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 20.072us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 35.126us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 11.000s | 143.476us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 129.664us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 306.551us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 35.126us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 129.664us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 34.000s | 4.009ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 16.000s | 624.653us | 5 | 5 | 100.00 |
| V1 | TOTAL | 159 | 166 | 95.78 | |||
| V2 | reset_recovery | otbn_reset | 36.000s | 172.724us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 49.000s | 188.704us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.000m | 506.945us | 7 | 10 | 70.00 |
| V2 | stress_all | otbn_stress_all | 1.533m | 4.236ms | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 1.183m | 346.835us | 47 | 60 | 78.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 16.968us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 22.000s | 159.641us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 20.702us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 13.322us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 9.000s | 237.835us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 9.000s | 237.835us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 20.072us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 35.126us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 129.664us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 28.027us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 20.072us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 35.126us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 129.664us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 28.027us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 227 | 246 | 92.28 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 107.443us | 9 | 10 | 90.00 |
| otbn_dmem_err | 10.000s | 28.936us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 53.000s | 910.113us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 28.000s | 117.972us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 14.000s | 41.012us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 10.000s | 43.583us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 30.474us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 23.409us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| otbn_tl_intg_err | 38.000s | 278.241us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 37.000s | 218.672us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | prim_count_check | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 8.000s | 36.765us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 10.000s | 28.936us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 107.443us | 9 | 10 | 90.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 38.000s | 278.241us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 1.183m | 346.835us | 47 | 60 | 78.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 107.443us | 9 | 10 | 90.00 |
| otbn_dmem_err | 10.000s | 28.936us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 9.000s | 16.968us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 30.474us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 107.443us | 9 | 10 | 90.00 |
| otbn_dmem_err | 10.000s | 28.936us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 9.000s | 16.968us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 30.474us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 1.183m | 346.835us | 47 | 60 | 78.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 107.443us | 9 | 10 | 90.00 |
| otbn_dmem_err | 10.000s | 28.936us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 9.000s | 16.968us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 30.474us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 21.304us | 10 | 12 | 83.33 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 28.297us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 38.000s | 251.476us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 38.000s | 251.476us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 10.000s | 19.314us | 7 | 10 | 70.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 13.000s | 43.444us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 9.000s | 13.251us | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 9.000s | 13.251us | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 7.000s | 15.953us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.000m | 506.945us | 7 | 10 | 70.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 18.000s | 364.880us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 44.000s | 187.084us | 93 | 100 | 93.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 5.100m | 1.443ms | 4 | 5 | 80.00 |
| V2S | TOTAL | 143 | 153 | 93.46 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 25.933m | 39.980ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 534 | 575 | 92.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 12 | 63.16 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.78 | 99.53 | 94.51 | 99.63 | 90.99 | 93.35 | 97.44 | 91.52 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 8 failures:
6.otbn_rf_base_intg_err.4210907157
Line 244, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 54133608 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 54133608 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 54133608 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 54133608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_rf_base_intg_err.374997404
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 201249269 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 201249269 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 201249269 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 201249269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
16.otbn_escalate.2228323591
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 74369259 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 74369259 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 74369259 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 74369259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.otbn_escalate.1639394127
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 3832435 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3832435 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3832435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_ctrl_redun has 2 failures.
0.otbn_ctrl_redun.487554547
Line 247, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7621294 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7621294 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 7621294 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7621294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_ctrl_redun.1735916842
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4342817 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 4342817 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4342817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stack_addr_integ_chk has 1 failures.
2.otbn_stack_addr_integ_chk.279112081
Line 247, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17263347 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 17263347 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 17263347 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17263347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
54.otbn_escalate.203922526
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/54.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 48173315 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 48173315 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 48173315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 4 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
7.otbn_stress_all_with_rand_reset.1935730344
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1007527072 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 1007527072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 3 failures.
30.otbn_single.4007228651
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_single/latest/run.log
UVM_FATAL @ 10864760 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 10864760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.otbn_single.633074057
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_single/latest/run.log
UVM_FATAL @ 173592010 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 173592010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 3 failures:
Test otbn_single has 2 failures.
3.otbn_single.3472490471
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_single/latest/run.log
UVM_FATAL @ 9588731 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9588731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.otbn_single.1878437842
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_single/latest/run.log
UVM_FATAL @ 19315155 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 19315155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 1 failures.
9.otbn_stress_all.3684673314
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log
UVM_FATAL @ 21779078 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 21779078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 3 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
6.otbn_stress_all_with_rand_reset.3257239087
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 50538785 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 50538785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 2 failures.
46.otbn_single.2766692090
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_single/latest/run.log
UVM_FATAL @ 15536548 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 15536548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
53.otbn_single.219342265
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_single/latest/run.log
UVM_FATAL @ 12844180 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 12844180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
44.otbn_escalate.499942237
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log
UVM_FATAL @ 22465059 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 22465059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.otbn_escalate.3326337919
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log
UVM_FATAL @ 11127502 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 11127502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
1.otbn_multi.1301593305
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_multi/latest/run.log
UVM_FATAL @ 849990068 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 849990068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_multi.3615111566
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_multi/latest/run.log
UVM_FATAL @ 63326604 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 63326604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
0.otbn_multi.3886285857
Line 277, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi/latest/run.log
UVM_FATAL @ 117908871 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 117908871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
0.otbn_imem_err.295028493
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_imem_err/latest/run.log
UVM_FATAL @ 9681737 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9681737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
0.otbn_escalate.51800688
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
UVM_FATAL @ 4304456 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 4304456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
0.otbn_stress_all_with_rand_reset.1588550950
Line 318, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 656081822 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 656081822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1258): Assertion InitSecWipeNonZeroWideRegs_A has failed has 1 failures:
0.otbn_zero_state_err_urnd.3432399702
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6412082 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[19].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6412082 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[18].InitSecWipeNonZeroWideRegs_A has failed
UVM_ERROR @ 6412082 ps: (otbn.sv:1258) [ASSERT FAILED] InitSecWipeNonZeroWideRegs_A
UVM_INFO @ 6412082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
1.otbn_stress_all_with_rand_reset.749061956
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 67667357 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 67667357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
2.otbn_dmem_err.857948583
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_dmem_err/latest/run.log
UVM_FATAL @ 13069000 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 13069000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1296): Assertion SecWipeNonZeroMod_A has failed has 1 failures:
4.otbn_sec_cm.4100950169
Line 218, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1296): (time 6674174 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1303): (time 6674174 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6674174 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6674174 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6674174 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
5.otbn_rf_bignum_intg_err.1358380361
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_rf_bignum_intg_err/latest/run.log
UVM_FATAL @ 16901506 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 16901506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
6.otbn_stress_all.472488500
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all/latest/run.log
UVM_FATAL @ 52047331 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 52047331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
8.otbn_stress_all_with_rand_reset.4251761134
Line 298, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 384535584 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 384535584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
9.otbn_escalate.4023240091
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
UVM_FATAL @ 14503846 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 14503846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
13.otbn_escalate.2458452802
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1435848 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1435848 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1435848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
23.otbn_escalate.2984280834
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log
UVM_FATAL @ 6976927 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 6976927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---