OTBN Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	126.755us	1	1	100.00
V1	single_binary	otbn_single	1.600m	371.895us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	57.702us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.360us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	275.772us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.104us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	40.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.104us	5	5	100.00
V1	mem_walk	otbn_mem_walk	34.000s	1.146ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	239.908us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	2.833m	1.388ms	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	328.947us	1	1	100.00
V2	back_to_back	otbn_multi	1.383m	731.301us	10	10	100.00
V2	stress_all	otbn_stress_all	4.883m	1.260ms	10	10	100.00
V2	lc_escalation	otbn_escalate	19.000s	87.250us	52	60	86.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	29.539us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	30.000s	218.707us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	49.032us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	27.499us	49	50	98.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	145.765us	19	20	95.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	145.765us	19	20	95.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	57.702us	5	5	100.00
		otbn_csr_rw	6.000s	16.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.104us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	44.798us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	57.702us	5	5	100.00
		otbn_csr_rw	6.000s	16.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.104us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	44.798us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	16.000s	55.781us	10	10	100.00
		otbn_dmem_err	17.000s	71.316us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	45.000s	383.359us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	61.179us	5	5	100.00
		otbn_mac_bignum_acc_err	26.000s	107.553us	5	5	100.00
		otbn_urnd_err	8.000s	70.424us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	36.731us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	83.597us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
		otbn_tl_intg_err	1.117m	522.869us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	42.000s	251.339us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	126.755us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	71.316us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	55.781us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.117m	522.869us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	19.000s	87.250us	52	60	86.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	55.781us	10	10	100.00
		otbn_dmem_err	17.000s	71.316us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.539us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	36.731us	5	5	100.00
		otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	55.781us	10	10	100.00
		otbn_dmem_err	17.000s	71.316us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.539us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	36.731us	5	5	100.00
		otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	19.000s	87.250us	52	60	86.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	55.781us	10	10	100.00
		otbn_dmem_err	17.000s	71.316us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.539us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	36.731us	5	5	100.00
		otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	39.992us	9	12	75.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	38.496us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	33.000s	130.955us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	33.000s	130.955us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	62.870us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	329.993us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.483m	10.006ms	2	5	40.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.483m	10.006ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	24.764us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.383m	731.301us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	48.626us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.600m	371.895us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	23.950m	9.502ms	5	5	100.00
V2S		TOTAL			146	153	95.42
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	14.433m	10.258ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			555	575	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.84	99.49	93.76	99.61	93.61	93.55	97.44	91.05	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_ctrl_redun has 1 failures.

5.otbn_ctrl_redun.90198376663316740471056512621611629041417230271336302684941530540146859365754
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7888390 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7888390 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7888390 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   7888390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

38.otbn_escalate.66187311661438379171095988880141176809057102382096724227091193723035163136173
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21023173 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21023173 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21023173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.otbn_escalate.62537493978037594290130080667751427555927727414388596289772872019343278743100
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/47.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 75581827 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  75581827 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  75581827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

6.otbn_escalate.6987542469268950813282106908247556767882759577332182110884573210802540479436
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7994040 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7994040 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   7994040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.otbn_escalate.27367071507191826902159865822439106053675546629642470958182778823252260234841
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2198114 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2198114 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2198114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 2.otbn_stack_addr_integ_chk.21221234970868935843477727702100208329506637850450787971421054526841445464071
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10005823209 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10005823209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stack_addr_integ_chk.7238789784558506006919175195344740692091851328647872724275108263272523797060
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10009936471 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10009936471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 2 failures:

Test otbn_ctrl_redun has 2 failures.

4.otbn_ctrl_redun.93672957353767014604787358338925746340437848405136088413626259963596396977874
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  28328358 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  28328358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_ctrl_redun.95533790829851666896248736452808134400865483573074471063111837812848378890571
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  29166005 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  29166005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

28.otbn_escalate.92059049483604547394603199675763347558584359642728612290269286173219659983019
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  UVM_FATAL @  48630011 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  48630011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.otbn_escalate.105846582376027932636406701862753980552995476695279635578034024151503076828535
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  UVM_FATAL @  27912142 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  27912142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:31) virtual_sequencer [otbn_rf_base_intg_err_vseq] Register file was not used before time limit has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.98850477230021318017298716306804863521582349438927746446009287680479390754021
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 442821696 ps: (otbn_rf_base_intg_err_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Register file was not used before time limit
  UVM_INFO @ 442821696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job otbn-sim-xcelium_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test otbn_tl_errors has 1 failures.
  - 0.otbn_tl_errors.28271681132110960693881704531581262494203494712974065419369914488260179377939
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_tl_errors/latest/run.log
```
  Job ID: smart:9ecb126a-3de7-4cc8-8bdb-0e2dbec50ec6
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.86383332091164511363172444298338902472446243048196245409630854526943924548548
    Line 391, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 583740966 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 583740966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.63527779400498788049513750753298764016714349160381243480800951482348790551647
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10002079372 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10002079372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.87349359272728424233839083586519835608598052159902070959043315002028925182302
    Line 352, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1921932695 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1921932695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.1379368756065785896990161186714478728606201452638221414420310261920272198803
    Line 321, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   9898283 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   9898283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 1 failures:

Test otbn_escalate has 1 failures.

7.otbn_escalate.105317971459802088915946124760713744911762003092225149931866489212407160833134
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 38190004 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38190004 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38190004 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  38190004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job otbn-sim-xcelium_run_cover_reg_top killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:
- Test otbn_intr_test has 1 failures.
  - 22.otbn_intr_test.30190805080630267027377378076692813177825096331206118621580075071512750362829
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_intr_test/latest/run.log
```
  Job ID: smart:37dcf292-1753-492e-9fa6-32f0bdf9683a
```