OTP_CTRL Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.520s	954.417us	1	1	100.00
V1	smoke	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.630s	1.383ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.940s	576.763us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.190s	1.913ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.920s	122.592us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.350s	205.766us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.940s	576.763us	20	20	100.00
		otp_ctrl_csr_aliasing	3.920s	122.592us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.290s	69.516us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.790s	539.767us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	15.550s	1.281ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.220s	2.301ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	23.640s	4.209ms	10	10	100.00
		otp_ctrl_check_fail	1.262m	9.140ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.520s	4.446ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	32.230s	10.135ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.690s	11.535ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	22.930s	6.687ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	32.200s	12.211ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.494m	12.234ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.351m	65.962ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.970s	543.733us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.840s	1.010ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.430s	678.420us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.430s	678.420us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.630s	1.383ms	5	5	100.00
		otp_ctrl_csr_rw	1.940s	576.763us	20	20	100.00
		otp_ctrl_csr_aliasing	3.920s	122.592us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.170s	109.231us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.630s	1.383ms	5	5	100.00
		otp_ctrl_csr_rw	1.940s	576.763us	20	20	100.00
		otp_ctrl_csr_aliasing	3.920s	122.592us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.170s	109.231us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
		otp_ctrl_tl_intg_err	19.880s	4.523ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	19.880s	4.523ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_macro_errs	32.200s	12.211ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_macro_errs	32.200s	12.211ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.790s	6.726ms	200	200	100.00
		otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.220s	2.301ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.262m	9.140ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	32.090s	13.227ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.396m	31.402ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.520s	4.446ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	11.840s	4.400ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	32.200s	12.211ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.900s	3.024ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.778h	4.223s	96	100	96.00
V3		TOTAL			97	101	96.04
		TOTAL			1339	1343	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.45	92.63	91.75	92.51	92.11	93.45	96.53	95.19

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 39.otp_ctrl_stress_all_with_rand_reset.1131130103
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:87226415-fb41-4444-9f20-d91e28298665
      

    • 76.otp_ctrl_stress_all_with_rand_reset.2864621316
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:cac36b5a-eec3-429a-9cff-df9c8d5f874e
      

    • ... and 1 more failures.

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.otp_ctrl_stress_all_with_rand_reset.4112383822
      Line 2105, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3336895399704 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 3336895399704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.20_19.32.03
• 2023.05.19_16.13.05
• 2023.05.18_19.15.40
• 2023.05.17_17.59.32
• 2023.05.16_19.23.36
• 2023.05.15_18.41.17
• 2023.05.14_18.09.01