748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 1.890s | 82.163us | 1 | 1 | 100.00 |
| V1 | smoke | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 2.470s | 1.016ms | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 2.220s | 633.290us | 17 | 20 | 85.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 9.930s | 4.379ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 3.860s | 216.409us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 3.650s | 1.058ms | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.220s | 633.290us | 17 | 20 | 85.00 |
| otp_ctrl_csr_aliasing | 3.860s | 216.409us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 2.080s | 516.713us | 4 | 5 | 80.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.340s | 60.471us | 4 | 5 | 80.00 |
| V1 | TOTAL | 100 | 116 | 86.21 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 17.450s | 3.114ms | 1 | 1 | 100.00 |
| V2 | init_fail | otp_ctrl_init_fail | 8.520s | 2.744ms | 288 | 300 | 96.00 |
| V2 | partition_check | otp_ctrl_background_chks | 21.230s | 2.302ms | 9 | 10 | 90.00 |
| otp_ctrl_check_fail | 41.420s | 15.887ms | 41 | 50 | 82.00 | ||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 12.040s | 3.747ms | 47 | 50 | 94.00 |
| V2 | partition_lock | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 24.050s | 2.475ms | 44 | 50 | 88.00 |
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 32.170s | 11.194ms | 48 | 50 | 96.00 |
| otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 | ||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 20.640s | 8.087ms | 41 | 50 | 82.00 |
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 26.840s | 1.832ms | 42 | 50 | 84.00 |
| V2 | test_access | otp_ctrl_test_access | 32.080s | 12.122ms | 49 | 50 | 98.00 |
| V2 | stress_all | otp_ctrl_stress_all | 4.764m | 19.292ms | 44 | 50 | 88.00 |
| V2 | intr_test | otp_ctrl_intr_test | 2.240s | 589.860us | 45 | 50 | 90.00 |
| V2 | alert_test | otp_ctrl_alert_test | 3.640s | 333.011us | 46 | 50 | 92.00 |
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 6.220s | 329.414us | 17 | 20 | 85.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 6.220s | 329.414us | 17 | 20 | 85.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 2.470s | 1.016ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.220s | 633.290us | 17 | 20 | 85.00 | ||
| otp_ctrl_csr_aliasing | 3.860s | 216.409us | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.290s | 266.526us | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 2.470s | 1.016ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.220s | 633.290us | 17 | 20 | 85.00 | ||
| otp_ctrl_csr_aliasing | 3.860s | 216.409us | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.290s | 266.526us | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 1015 | 1101 | 92.19 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| otp_ctrl_tl_intg_err | 19.320s | 1.675ms | 16 | 20 | 80.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 19.320s | 1.675ms | 16 | 20 | 80.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_macro_errs | 26.840s | 1.832ms | 42 | 50 | 84.00 | ||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_macro_errs | 26.840s | 1.832ms | 42 | 50 | 84.00 | ||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 11.250s | 1.460ms | 191 | 200 | 95.50 |
| otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 8.520s | 2.744ms | 288 | 300 | 96.00 |
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 41.420s | 15.887ms | 41 | 50 | 82.00 |
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 32.520s | 13.498ms | 45 | 50 | 90.00 |
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 3.171m | 34.482ms | 5 | 5 | 100.00 |
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 12.040s | 3.747ms | 47 | 50 | 94.00 |
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 9.050s | 1.090ms | 42 | 50 | 84.00 |
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 26.840s | 1.832ms | 42 | 50 | 84.00 |
| V2S | TOTAL | 21 | 25 | 84.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 19.680s | 7.582ms | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 2.837h | 1.406s | 89 | 100 | 89.00 |
| V3 | TOTAL | 90 | 101 | 89.11 | |||
| TOTAL | 1226 | 1343 | 91.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 3 | 33.33 |
| V2 | 17 | 17 | 1 | 5.88 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.28 | 92.55 | 91.03 | 92.21 | 92.11 | 93.28 | 96.53 | 95.27 |
Exit reason: Error: User command failed Job returned non-zero exit code has 110 failures:
Test otp_ctrl_mem_partial_access has 1 failures.
0.otp_ctrl_mem_partial_access.74947540744192371488242788815715991271321373685861226241916440166173502652427
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest/run.log
[make]: simulate
cd /workspace/0.otp_ctrl_mem_partial_access/latest && /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922692619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.2922692619
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test otp_ctrl_mem_walk has 1 failures.
1.otp_ctrl_mem_walk.63990604095926819389490596057747730713317033943964933733122434746592242580110
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest/run.log
[make]: simulate
cd /workspace/1.otp_ctrl_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085684366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.1085684366
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test otp_ctrl_tl_intg_err has 4 failures.
2.otp_ctrl_tl_intg_err.100359195145167045541359441565455993319585158302586952586871557863449341693281
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/2.otp_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655410017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1655410017
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
14.otp_ctrl_tl_intg_err.15949954508000981522140007213363429332560685988116645271564048614849321677800
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/14.otp_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780162536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.3780162536
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more failures.
Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
2.otp_ctrl_csr_mem_rw_with_rand_reset.100898383425330171754207975699741940795445869683730917299762483267651282529246
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544495582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.2544495582
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
16.otp_ctrl_csr_mem_rw_with_rand_reset.5493734291161000468380819547023685524380061619202773127604937232420213581280
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246693344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.4246693344
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test otp_ctrl_background_chks has 1 failures.
3.otp_ctrl_background_chks.78098732549439335255701739371518838418484223056241868512046489480155835804224
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest/run.log
[make]: simulate
cd /workspace/3.otp_ctrl_background_chks/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563044416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1563044416
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:54 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 19 more tests.
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
62.otp_ctrl_stress_all_with_rand_reset.57617501929564672294218370790172020731633590523809775910922364033644287601305
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:fed10de7-6ce7-4441-aa24-f14aa912b4f0
69.otp_ctrl_stress_all_with_rand_reset.82391593562161934744893449311289883307609176806369760651347446494114040398631
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:13954208-7ec4-4c06-a323-cdb9601df523
... and 1 more failures.
Job otp_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
7.otp_ctrl_csr_rw.95644396607900978109729210582619007813963525979940478586275763840971477168205
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest/run.log
Job ID: smart:05d54a44-bdc0-45d5-8bbe-a39fb274061c
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12850956) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.otp_ctrl_stress_all_with_rand_reset.76041951903409995059435608527611507537499868851430351659843308600735368192080
Line 751, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126249523423 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12850956) { a_addr: 'hf99299bc a_data: 'h69d8d9e2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h0 a_user: 'h24ca8 d_param: 'h0 d_source: 'h3b d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 126249523423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' has 1 failures:
19.otp_ctrl_stress_all_with_rand_reset.7627809179777704024172090245389479505805567359858332315663714687139189751003
Line 2793, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 2996166472381 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 2996166472381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1561634) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
42.otp_ctrl_stress_all.53827182763849485171527907044944778726604733801395708044646651166752591607117
Line 352, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest/run.log
UVM_ERROR @ 10283645677 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1561634) { a_addr: 'hc4427cb0 a_data: 'h2f337747 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h0 a_user: 'h25f98 d_param: 'h0 d_source: 'hc d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 10283645677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---