OTP_CTRL Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	117.004us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.600s	358.589us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.310s	587.616us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.220s	6.414ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.480s	115.438us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.000s	1.640ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.310s	587.616us	20	20	100.00
		otp_ctrl_csr_aliasing	3.480s	115.438us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.480s	135.464us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.110s	517.542us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	34.800s	9.916ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.690s	2.920ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	13.990s	2.488ms	10	10	100.00
		otp_ctrl_check_fail	28.000s	12.967ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	8.640s	567.148us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	25.390s	7.446ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.080s	10.013ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	17.870s	2.434ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.477m	9.107ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	40.670s	15.311ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	5.010m	53.277ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	579.346us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.390s	655.905us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.930s	3.206ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.930s	3.206ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.600s	358.589us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	587.616us	20	20	100.00
		otp_ctrl_csr_aliasing	3.480s	115.438us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.090s	118.977us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.600s	358.589us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	587.616us	20	20	100.00
		otp_ctrl_csr_aliasing	3.480s	115.438us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.090s	118.977us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.460s	18.308ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.460s	18.308ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_macro_errs	1.477m	9.107ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_macro_errs	1.477m	9.107ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.190s	6.732ms	200	200	100.00
		otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.690s	2.920ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	28.000s	12.967ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	33.890s	3.840ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.590m	138.481ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	8.640s	567.148us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.090s	5.254ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.477m	9.107ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.560s	5.942ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.846h	5.528s	93	100	93.00
V3		TOTAL			94	101	93.07
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.25	92.63	91.00	92.41	91.55	93.33	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.89213814563258476462869844535392892261707978403274909252626516701823069098277
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c7d21854-82a6-42b0-b5b0-4d64ed8a4402
```
  - 50.otp_ctrl_stress_all_with_rand_reset.23565756323567952721924663468483514347537506694773704052784738559275526270849
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a3f31686-9828-4755-86c9-22928cad9dd3
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 5.otp_ctrl_csr_mem_rw_with_rand_reset.90369063982635365426570333597655654239542127112698353853776800943876180007987
    Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  36652446 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  36652446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 10.otp_ctrl_csr_mem_rw_with_rand_reset.5314912472584131917043963762178170804594292774985755846365066693687257199876
    Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26523203 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26523203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@114512) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

14.otp_ctrl_test_access.65625860238521686640195515861595178008823689976155556431904382795770499389202
Line 270, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 7884313474 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@114512) { a_addr: 'h715e44b0  a_data: 'ha67f7cfa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hef  a_opcode: 'h0  a_user: 'h27108  d_param: 'h0  d_source: 'hef  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 7884313474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@21568849) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 88.otp_ctrl_stress_all_with_rand_reset.11323539494546126242953816920859589291785846027104024558158692000732228607004
    Line 1090, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132302060741 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@21568849) { a_addr: 'h3ef69250  a_data: 'he3552b24  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h50  a_opcode: 'h1  a_user: 'h25cc2  d_param: 'h0  d_source: 'h50  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 132302060741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

89.otp_ctrl_stress_all_with_rand_reset.57728249788044523818389233864762368671232092353816164111301804617246108309997
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321832429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2321832429
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 17 13:45 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255