OTP_CTRL Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.980s	235.859us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.210s	972.175us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.900s	528.619us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.870s	429.523us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.200s	260.637us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.790s	1.114ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.900s	528.619us	20	20	100.00
		otp_ctrl_csr_aliasing	4.200s	260.637us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	131.961us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	134.379us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.000s	627.510us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.580s	2.661ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	52.840s	7.275ms	10	10	100.00
		otp_ctrl_check_fail	47.220s	14.893ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.370s	280.401us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	29.450s	10.824ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.130s	10.363ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	24.770s	10.015ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	30.860s	12.775ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	44.380s	4.517ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	11.631m	65.724ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.090s	551.223us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.160s	281.344us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.580s	2.530ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.580s	2.530ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.210s	972.175us	5	5	100.00
		otp_ctrl_csr_rw	1.900s	528.619us	20	20	100.00
		otp_ctrl_csr_aliasing	4.200s	260.637us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.270s	215.948us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.210s	972.175us	5	5	100.00
		otp_ctrl_csr_rw	1.900s	528.619us	20	20	100.00
		otp_ctrl_csr_aliasing	4.200s	260.637us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.270s	215.948us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
		otp_ctrl_tl_intg_err	43.650s	19.245ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	43.650s	19.245ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_macro_errs	30.860s	12.775ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_macro_errs	30.860s	12.775ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.980s	1.759ms	200	200	100.00
		otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.580s	2.661ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.220s	14.893ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	29.240s	5.985ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.420m	35.939ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.370s	280.401us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.920s	5.875ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	30.860s	12.775ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.830s	2.992ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.835h	5.011s	88	100	88.00
V3		TOTAL			89	101	88.12
		TOTAL			1330	1343	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.51	92.55	91.52	92.59	92.68	93.44	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 41.otp_ctrl_stress_all_with_rand_reset.1002047857449672743233855183144541450713306451196090461254462395635147630121
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5eddd3c5-fd42-40cc-94bd-7217251a4459
```
  - 71.otp_ctrl_stress_all_with_rand_reset.98912982827861144646614651557917089357596522039648383570771617349451688358901
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3200944d-e0ae-438e-be30-d7e4a8be5ac9
```
  - ... and 4 more failures.
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 22.otp_ctrl_stress_all_with_rand_reset.103067452628257247479755981705518602512099262040382462157276606379995488232282
    Line 271, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234684059 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 234684059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.otp_ctrl_stress_all_with_rand_reset.16437364523523858475810568161323712300478028240529887898475787406137282976709
    Line 803, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2047904070824 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2047904070824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@62804) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

1.otp_ctrl_test_access.46372781339523587931820350242345877980531879453998250184840192843032801634689
Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 436548787 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@62804) { a_addr: 'h27f8cf8c  a_data: 'hb0216547  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha2  a_opcode: 'h1  a_user: 'h265da  d_param: 'h0  d_source: 'ha2  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 436548787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@78271) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.27466489462947619899516299806832476039847386346581172554568331541312859026350
    Line 274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1395002527 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@78271) { a_addr: 'h19fc3868  a_data: 'h9e000a52  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7a  a_opcode: 'h1  a_user: 'h264b1  d_param: 'h0  d_source: 'h7a  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 1395002527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.35408863424766827039426294605488950770075163842517212019191546997297361751419
    Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26853435 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26853435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@88745133) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.39240218383252869428175297368774082021623643418484484023735775487521868668342
    Line 3010, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 657833237182 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@88745133) { a_addr: 'hd8e6e3d4  a_data: 'h20efab87  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hee  a_opcode: 'h1  a_user: 'h24f7d  d_param: 'h0  d_source: 'hee  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 657833237182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@23680230) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 68.otp_ctrl_stress_all_with_rand_reset.44396061293914482258101207395912396813432719075377238170792803781707260668086
    Line 996, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58849824550 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@23680230) { a_addr: 'h555e0720  a_data: 'h717225e6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h0  a_user: 'h26fbb  d_param: 'h0  d_source: 'h26  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 58849824550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```