OTP_CTRL Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.670s	53.803us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.490s	196.886us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.280s	651.656us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	18.780s	6.379ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	10.170s	3.170ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.300s	71.780us	10	20	50.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.280s	651.656us	20	20	100.00
		otp_ctrl_csr_aliasing	10.170s	3.170ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.650s	553.960us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.760s	532.164us	5	5	100.00
V1		TOTAL			106	116	91.38
V2	dai_access_partition_walk	otp_ctrl_partition_walk	34.860s	12.922ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.690s	2.889ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	46.400s	16.127ms	10	10	100.00
		otp_ctrl_check_fail	2.208m	29.151ms	47	50	94.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.280s	4.652ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.630s	4.304ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.020s	7.260ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.560s	24.933ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.100m	24.783ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	48.120s	4.148ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.590m	28.510ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.320s	590.638us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.300s	941.925us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.610s	2.498ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.610s	2.498ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.490s	196.886us	5	5	100.00
		otp_ctrl_csr_rw	2.280s	651.656us	20	20	100.00
		otp_ctrl_csr_aliasing	10.170s	3.170ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.890s	1.835ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.490s	196.886us	5	5	100.00
		otp_ctrl_csr_rw	2.280s	651.656us	20	20	100.00
		otp_ctrl_csr_aliasing	10.170s	3.170ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.890s	1.835ms	20	20	100.00
V2		TOTAL			1097	1101	99.64
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.420s	4.997ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.420s	4.997ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_macro_errs	1.100m	24.783ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_macro_errs	1.100m	24.783ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.490s	16.824ms	200	200	100.00
		otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.690s	2.889ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.208m	29.151ms	47	50	94.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	59.540s	6.203ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.169m	173.322ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.280s	4.652ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.160s	6.946ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.100m	24.783ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.880s	5.925ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.702h	6.635s	62	100	62.00
V3		TOTAL			63	101	62.38
		TOTAL			1291	1343	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.98	93.91	96.64	95.79	91.41	97.42	96.33	93.35

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 24 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.36381304380430297628856455427822090223136795586068037234898835413706700240976
    Line 268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1875661886 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1875661886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otp_ctrl_stress_all_with_rand_reset.110501998067580079566478839100727738159261816990890221737375738903095701655904
    Line 29221, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 218660193127 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 218660193127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_vseq.sv:719) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 16 failures:

Test otp_ctrl_csr_mem_rw_with_rand_reset has 9 failures.

0.otp_ctrl_csr_mem_rw_with_rand_reset.41829869875877080535992228767041010829764712784474752127959593186178641346668
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 596810495 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 596810495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otp_ctrl_csr_mem_rw_with_rand_reset.108190157043920701121419304798129943248217597745483713624379379472808919928822
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  41206340 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  41206340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

2.otp_ctrl_stress_all_with_rand_reset.28598850518304757353414030055298378025211720677695565289746411382327018012882
Line 36514, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 135956279015 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 135956279015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.otp_ctrl_stress_all_with_rand_reset.108478572986954524252825274237175157349334811489234343582004989772847441540014
Line 21662, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1667093938996 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1667093938996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.104359414467991900030993738350976433075778016120623069972769880788254354765581
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:155e7c70-a03c-405d-8563-257ff58c2e52
```
  - 31.otp_ctrl_stress_all_with_rand_reset.40067231677009365001994905141973875972027554775848172859782639928564883016778
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1d45d30f-86f6-4a21-b83f-4fd55f294675
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 3 failures:
- Test otp_ctrl_check_fail has 3 failures.
  - 0.otp_ctrl_check_fail.39901055387914148297628387140401295461771832727399034099045420372425129060826
    Line 10394, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 7206244313 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 7206244313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.otp_ctrl_check_fail.19204840395136104827052506092846124267623512758526496866292246467538336619453
    Line 11135, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 581903790 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 581903790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.otp_ctrl_csr_mem_rw_with_rand_reset.36425984194822254299566167717017399678727101245233837116085515284191862423691
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 986035992 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 986035992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2000914) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

9.otp_ctrl_stress_all.76742621841139483505933898890753072140205312175821171109207533023147267010745
Line 88253, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 18483843529 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2000914) { a_addr: 'h8f366564  a_data: 'h63c82444  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h0  a_user: 'h2717d  d_param: 'h0  d_source: 'h5  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 18483843529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 85.otp_ctrl_stress_all_with_rand_reset.50615486738552248302090763150484759938590694823083684338997421881576451041965
    Line 792, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1692061854 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1692061854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```