OTP_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	53.366us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.470s	202.755us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.290s	568.368us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.480s	1.025ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.940s	2.998ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.130s	1.104ms	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.290s	568.368us	20	20	100.00
		otp_ctrl_csr_aliasing	8.940s	2.998ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	39.589us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.680s	511.642us	5	5	100.00
V1		TOTAL			112	116	96.55
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.240s	315.130us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.940s	2.321ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	39.760s	5.987ms	10	10	100.00
		otp_ctrl_check_fail	56.010s	7.983ms	44	50	88.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.880s	5.146ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.287m	3.350ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.520s	10.841ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	53.790s	17.516ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	59.890s	19.917ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.401m	13.219ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	6.353m	93.215ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.820s	594.676us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.860s	268.375us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.410s	2.450ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.410s	2.450ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.470s	202.755us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	568.368us	20	20	100.00
		otp_ctrl_csr_aliasing	8.940s	2.998ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.120s	480.016us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.470s	202.755us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	568.368us	20	20	100.00
		otp_ctrl_csr_aliasing	8.940s	2.998ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.120s	480.016us	20	20	100.00
V2		TOTAL			1093	1101	99.27
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
		otp_ctrl_tl_intg_err	31.750s	19.865ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	31.750s	19.865ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_macro_errs	59.890s	19.917ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_macro_errs	59.890s	19.917ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.700s	1.997ms	200	200	100.00
		otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.940s	2.321ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	56.010s	7.983ms	44	50	88.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	59.180s	28.496ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.933m	170.371ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.880s	5.146ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.260s	3.851ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	59.890s	19.917ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.610s	3.007ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.743h	1.715s	63	100	63.00
V3		TOTAL			64	101	63.37
		TOTAL			1294	1343	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	14	82.35
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.04	94.00	96.69	95.77	91.65	97.56	96.33	93.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:815) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 24 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.36494325518944493330854266814474036520761044896670702368580974685799900834134
    Line 2469, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 135528221 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 135528221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otp_ctrl_stress_all_with_rand_reset.16602025813578448845663903632664807571840777451077543723786098791588565758895
    Line 23177, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112672766777 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112672766777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_vseq.sv:741) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 8 failures:

Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

1.otp_ctrl_stress_all_with_rand_reset.76251437823186360652878420933436093545121176708695215633328833877068962853891
Line 9904, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 455850816365 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 455850816365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otp_ctrl_stress_all_with_rand_reset.50731478258571000733563220728922954711312717975383090996898521748235439444865
Line 7687, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2022893144825 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2022893144825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test otp_ctrl_csr_mem_rw_with_rand_reset has 4 failures.

1.otp_ctrl_csr_mem_rw_with_rand_reset.73817497414075188889541672094534482365345298049780026610620943972692594301884
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  89685241 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  89685241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otp_ctrl_csr_mem_rw_with_rand_reset.68138464365373866504752844880274878204956749975291901050799204886556943907830
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  37194336 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  37194336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 6 failures:
- Test otp_ctrl_check_fail has 6 failures.
  - 0.otp_ctrl_check_fail.33839168533620970067064646100679432181452250039078404744134644794190287252608
    Line 1538, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 2577337443 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 2577337443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otp_ctrl_check_fail.28169900166612425154965246558734269209779067108380456616069539443967419370297
    Line 5124, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 372272218 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 372272218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.65581727480992756989348601292064867353874341352607034102971516324903900969166
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f1bae66e-7daa-4198-8da8-21f59e04ec30
```
  - 27.otp_ctrl_stress_all_with_rand_reset.86768677129681265925213512973554775328662827156955158472270223820372221138461
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ef164f5c-8b14-4c3e-b6e5-1f8a69ee8015
```
  - ... and 2 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.80072266283379891402306868364770971236981227202137365530923252788123543408151
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  53991621 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  53991621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 35.otp_ctrl_stress_all_with_rand_reset.92677699602690964995836533025598422510186543313569982430266522778808450875430
    Line 10798, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1147406566 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1147406566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

11.otp_ctrl_stress_all_with_rand_reset.34879604704538142300570250703341105773504650850693999212049739031022017188163
Line 1671, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 151483736 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 151504354 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 151514663 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 151803315 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 151813624 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@188005) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

13.otp_ctrl_test_access.95447576045918048708841722343063430507637416405701789371828863833761204924016
Line 10803, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 7259734469 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@188005) { a_addr: 'h1908e584  a_data: 'hdcd906aa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h0  a_user: 'h27193  d_param: 'h0  d_source: 'h24  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 7259734469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2044301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

26.otp_ctrl_stress_all.12296751115778110794250866224025264779944090599061029044758385751356598510859
Line 115784, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8822742950 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2044301) { a_addr: 'h897377dc  a_data: 'h5429ff99  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4b  a_opcode: 'h0  a_user: 'h27a2c  d_param: 'h0  d_source: 'h4b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 8822742950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 56.otp_ctrl_stress_all_with_rand_reset.15707334744285904184212008673711463742107411181734739184399407762258270368228
    Line 5080, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 627491164 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 627491164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```