OTP_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.380s	776.600us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.740s	375.437us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.230s	598.937us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.980s	510.587us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.310s	210.663us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.670s	1.572ms	12	20	60.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.230s	598.937us	20	20	100.00
		otp_ctrl_csr_aliasing	6.310s	210.663us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.960s	543.099us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.730s	511.459us	5	5	100.00
V1		TOTAL			108	116	93.10
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.150s	1.608ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.910s	2.994ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	59.160s	23.654ms	10	10	100.00
		otp_ctrl_check_fail	41.300s	13.671ms	49	50	98.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.890s	5.016ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.630s	19.420ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	42.600s	14.440ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.126m	17.586ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	57.330s	6.876ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.635m	17.352ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	6.325m	61.554ms	48	50	96.00
V2	intr_test	otp_ctrl_intr_test	2.030s	518.916us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.970s	795.624us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.210s	3.146ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.210s	3.146ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.740s	375.437us	5	5	100.00
		otp_ctrl_csr_rw	2.230s	598.937us	20	20	100.00
		otp_ctrl_csr_aliasing	6.310s	210.663us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.470s	2.181ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.740s	375.437us	5	5	100.00
		otp_ctrl_csr_rw	2.230s	598.937us	20	20	100.00
		otp_ctrl_csr_aliasing	6.310s	210.663us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.470s	2.181ms	20	20	100.00
V2		TOTAL			1097	1101	99.64
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
		otp_ctrl_tl_intg_err	24.430s	2.051ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	24.430s	2.051ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_macro_errs	57.330s	6.876ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_macro_errs	57.330s	6.876ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.590s	16.356ms	200	200	100.00
		otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.910s	2.994ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	41.300s	13.671ms	49	50	98.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.158m	12.844ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.391m	20.868ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.890s	5.016ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.360s	4.500ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	57.330s	6.876ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.880s	5.969ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.897h	1.048s	54	100	54.00
V3		TOTAL			55	101	54.46
		TOTAL			1285	1343	95.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	14	82.35
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.00	93.94	96.66	95.61	91.65	97.51	96.33	93.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 30 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.73197010659458651101203755745834987797122180250758082024848400251739052261514
    Line 32228, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 734195202949 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 734195202949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otp_ctrl_stress_all_with_rand_reset.28843815960627298050999054078727057037004369582269161797504988256864955868361
    Line 26274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 470642496525 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 470642496525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 17 failures:

Test otp_ctrl_csr_mem_rw_with_rand_reset has 8 failures.

0.otp_ctrl_csr_mem_rw_with_rand_reset.40042602206817780370904000386735423818705114065887924939766881313771532774866
Line 278, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 144045775 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 144045775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otp_ctrl_csr_mem_rw_with_rand_reset.22009929053011884210657909427226898138287132227455961404696979224792272006841
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  73360309 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  73360309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

1.otp_ctrl_stress_all_with_rand_reset.109107398985461184804612466973057990150437565544240166814147780249768728474803
Line 4733, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 834309274011 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 834309274011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otp_ctrl_stress_all_with_rand_reset.84325963686745379738442478786664412878896325392099523041421603343286040338057
Line 75657, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1047657364939 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1047657364939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 34.otp_ctrl_stress_all_with_rand_reset.58631283614918109368529161263471107986535085058910536426199895666004322598828
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a3075324-5024-42cf-938b-3fcc41cc018c
```
  - 36.otp_ctrl_stress_all_with_rand_reset.33368603049729816910822478435625791508589428603787473127418214291587558959198
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ae3d3acd-ab99-499b-8172-eea11e0dee47
```
  - ... and 4 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@339787) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

12.otp_ctrl_test_access.78783537567223436927755149743699404108032266548165975117102187978348383716464
Line 21479, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 6882868470 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@339787) { a_addr: 'h4491075c  a_data: 'h1a12aca1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha8  a_opcode: 'h1  a_user: 'h2496e  d_param: 'h0  d_source: 'ha8  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 6882868470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 1 failures:
- Test otp_ctrl_check_fail has 1 failures.
  - 29.otp_ctrl_check_fail.9636576224824443378248542855510413008074794720604632061433524526399335626201
    Line 10117, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 1024140214 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 1024140214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@482246) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

34.otp_ctrl_stress_all.113643500623871543767476207745221005352483480092113436396896146784106753440787
Line 20664, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 5067554771 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@482246) { a_addr: 'h5969b2f4  a_data: 'h663d5e64  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h0  a_user: 'h26ce9  d_param: 'h0  d_source: 'h2d  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 5067554771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@509074) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

41.otp_ctrl_stress_all.43574903587990676523446521262140995521741304792870362287477248654445166635422
Line 30823, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 18132641228 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@509074) { a_addr: 'hb3bc1084  a_data: 'ha4bbb38a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb1  a_opcode: 'h1  a_user: 'h2780f  d_param: 'h0  d_source: 'hb1  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 18132641228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@542498) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 73.otp_ctrl_stress_all_with_rand_reset.13369298155876239369351783391752575712277167513029182086413657230259278733736
    Line 14456, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16573550710 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@542498) { a_addr: 'hcfe6ddc  a_data: 'hb492d3ef  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h65  a_opcode: 'h1  a_user: 'h24e6f  d_param: 'h0  d_source: 'h65  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 16573550710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```