OTP_CTRL Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: 1f410ef5dc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 0 1 0.00
V1 smoke otp_ctrl_smoke 0 50 0.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 0 5 0.00
V1 csr_rw otp_ctrl_csr_rw 0 20 0.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 0 5 0.00
V1 csr_aliasing otp_ctrl_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 0 20 0.00
otp_ctrl_csr_aliasing 0 5 0.00
V1 mem_walk otp_ctrl_mem_walk 0 5 0.00
V1 mem_partial_access otp_ctrl_mem_partial_access 0 5 0.00
V1 TOTAL 0 116 0.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 0 1 0.00
V2 init_fail otp_ctrl_init_fail 0 300 0.00
V2 partition_check otp_ctrl_background_chks 0 10 0.00
otp_ctrl_check_fail 0 50 0.00
V2 regwen_during_otp_init otp_ctrl_regwen 0 50 0.00
V2 partition_lock otp_ctrl_dai_lock 0 50 0.00
V2 interface_key_check otp_ctrl_parallel_key_req 0 50 0.00
V2 lc_interactions otp_ctrl_parallel_lc_req 0 50 0.00
otp_ctrl_parallel_lc_esc 0 200 0.00
V2 otp_dai_errors otp_ctrl_dai_errs 0 50 0.00
V2 otp_macro_errors otp_ctrl_macro_errs 0 50 0.00
V2 test_access otp_ctrl_test_access 0 50 0.00
V2 stress_all otp_ctrl_stress_all 0 50 0.00
V2 intr_test otp_ctrl_intr_test 0 50 0.00
V2 alert_test otp_ctrl_alert_test 0 50 0.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 0 20 0.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 0 20 0.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 0 5 0.00
otp_ctrl_csr_rw 0 20 0.00
otp_ctrl_csr_aliasing 0 5 0.00
otp_ctrl_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 0 5 0.00
otp_ctrl_csr_rw 0 20 0.00
otp_ctrl_csr_aliasing 0 5 0.00
otp_ctrl_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 1101 0.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 0 5 0.00
V2S tl_intg_err otp_ctrl_sec_cm 0 5 0.00
otp_ctrl_tl_intg_err 0 20 0.00
V2S prim_count_check otp_ctrl_sec_cm 0 5 0.00
V2S prim_fsm_check otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 0 20 0.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 0 50 0.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 0 50 0.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_macro_errs 0 50 0.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_macro_errs 0 50 0.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 0 200 0.00
otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 0 300 0.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 0 50 0.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 0 50 0.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 0 50 0.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 0 50 0.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 0 5 0.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 0 50 0.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 0 50 0.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 0 50 0.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 0 50 0.00
V2S TOTAL 0 25 0.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 0 1 0.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 0 100 0.00
V3 TOTAL 0 101 0.00
TOTAL 0 1343 0.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 0 0.00
V2 17 17 0 0.00
V2S 2 2 0 0.00
V3 2 2 0 0.00

Failure Buckets

Past Results