OTP_CTRL Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.690s	201.125us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.000s	1.548ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.590s	702.432us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.030s	3.491ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.060s	1.195ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.980s	271.852us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.590s	702.432us	20	20	100.00
		otp_ctrl_csr_aliasing	6.060s	1.195ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.500s	110.560us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.400s	71.020us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.430s	1.577ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.550s	2.672ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.600s	3.326ms	10	10	100.00
		otp_ctrl_check_fail	47.380s	8.613ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.050s	4.796ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.860s	12.266ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.610s	10.916ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	43.580s	15.747ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.716m	35.783ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	51.810s	1.955ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.022m	64.067ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.220s	571.420us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.570s	133.597us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.940s	1.316ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.940s	1.316ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.000s	1.548ms	5	5	100.00
		otp_ctrl_csr_rw	2.590s	702.432us	20	20	100.00
		otp_ctrl_csr_aliasing	6.060s	1.195ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.140s	1.869ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.000s	1.548ms	5	5	100.00
		otp_ctrl_csr_rw	2.590s	702.432us	20	20	100.00
		otp_ctrl_csr_aliasing	6.060s	1.195ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.140s	1.869ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.270s	18.949ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.270s	18.949ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_macro_errs	1.716m	35.783ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_macro_errs	1.716m	35.783ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.150s	4.742ms	200	200	100.00
		otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.550s	2.672ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.380s	8.613ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	49.890s	17.723ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.520m	10.841ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.050s	4.796ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.930s	3.525ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.716m	35.783ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.820s	6.890ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.098h	1.951s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.94	93.89	96.45	95.76	91.89	97.05	96.33	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 27.otp_ctrl_stress_all_with_rand_reset.14518722101037713809308577111789529421758987977333660353113006327022290097771
    Line 31764, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36684012297 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 36684012297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.otp_ctrl_stress_all_with_rand_reset.43817345378068912415208855653619679532998538736666715110268601466489211609239
    Line 16085, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29597421839 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 29597421839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.6174308350437667410518556573103892209284317376473381485713678500217079601906
    Line 30317, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64754492920 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1225033754 [0x4904881a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 64754492920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.otp_ctrl_stress_all_with_rand_reset.93636371853800270814147265478607131370320557918194362918603946347009782286017
    Line 90627, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 363663794539 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3126793740 [0xba5f160c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 363663794539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.34592795766117166899299377639890004455228772114237574054967021843214276013349
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 429817057 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 429817057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 76.otp_ctrl_stress_all_with_rand_reset.106839999429383743554818243907380090239711057297989595921835475606432197789993
    Line 16288, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 5882188061 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 5882188061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 40.otp_ctrl_stress_all_with_rand_reset.96215046191426804379636149424158787970629144691498167559236642935322628305040
    Line 102904, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 490867700436 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 600 [0x258]) dai addr 258 rdata0 readout mismatch
  UVM_INFO @ 490867700436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.otp_ctrl_stress_all_with_rand_reset.74202545048955101695030693282951942428381261153792621852017473490918451187459
    Line 268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 456382091 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 120 [0x78]) dai addr 78 rdata0 readout mismatch
  UVM_INFO @ 456382091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

34.otp_ctrl_stress_all_with_rand_reset.94812890648235504403064961092002935369760022881381104401825790772123328372739
Line 7557, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 773357306 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 773530774 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 773551182 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 773765466 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 773775670 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1