OTP_CTRL Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	56.865us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.510s	1.026ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.960s	136.019us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.620s	381.933us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.920s	650.468us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.170s	109.929us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.960s	136.019us	20	20	100.00
		otp_ctrl_csr_aliasing	6.920s	650.468us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.460s	48.004us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.590s	524.104us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.690s	618.826us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.700s	2.523ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.800s	2.225ms	10	10	100.00
		otp_ctrl_check_fail	1.714m	17.040ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.040s	5.397ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.091m	27.875ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.060s	9.319ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.830s	16.785ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	3.448m	24.832ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	47.330s	4.317ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	22.958m	217.170ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.200s	549.436us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.680s	300.859us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.000s	319.757us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.000s	319.757us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.510s	1.026ms	5	5	100.00
		otp_ctrl_csr_rw	1.960s	136.019us	20	20	100.00
		otp_ctrl_csr_aliasing	6.920s	650.468us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.480s	1.932ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.510s	1.026ms	5	5	100.00
		otp_ctrl_csr_rw	1.960s	136.019us	20	20	100.00
		otp_ctrl_csr_aliasing	6.920s	650.468us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.480s	1.932ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.690s	19.783ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.690s	19.783ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_macro_errs	3.448m	24.832ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_macro_errs	3.448m	24.832ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.830s	12.423ms	200	200	100.00
		otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.700s	2.523ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.714m	17.040ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.882m	26.868ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.689m	154.692ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.040s	5.397ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.600s	5.535ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	3.448m	24.832ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.430s	7.582ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.451h	2.608s	87	100	87.00
V3		TOTAL			88	101	87.13
		TOTAL			1330	1343	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.84	93.89	96.28	95.77	91.17	97.10	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 34.otp_ctrl_stress_all_with_rand_reset.77597653770933894424761247689960818699865766399797262183922979124651927914892
    Line 354, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  36039358 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  36039358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.otp_ctrl_stress_all_with_rand_reset.109908114012949568980553744621342206698513678090570491717307823949667153550046
    Line 11209, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83054160054 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 83054160054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 45.otp_ctrl_stress_all_with_rand_reset.63551393348250314043426105227905158363413601465879221888736813111380996126107
    Line 16263, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17347846704 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3348504639 [0xc796203f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 17347846704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 81.otp_ctrl_stress_all_with_rand_reset.26592569561144175243009459308987043175491035288850514624417768104087137750499
    Line 7599, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 167848465706 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3457903658 [0xce1b6c2a] vs 3151488726 [0xbbd7e6d6]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 167848465706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 48.otp_ctrl_stress_all_with_rand_reset.115181190470580772568810527203920493064442831348578281981169464060027738581292
    Line 56148, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130570884559 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 548 [0x224]) dai addr 224 rdata0 readout mismatch
  UVM_INFO @ 130570884559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 92.otp_ctrl_stress_all_with_rand_reset.26720060648875898928788979074913425724013800366313668480166782095056317281481
    Line 35705, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 762418065148 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 4028082060 [0xf017a78c]) dai addr 764 rdata0 readout mismatch
  UVM_INFO @ 762418065148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

83.otp_ctrl_stress_all_with_rand_reset.92768861602989242072354885813978419577060679900508361649702788552792419470369
Line 61201, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 276115834052 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 276115930826 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 276116769534 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 276116801792 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 276117963080 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

99.otp_ctrl_stress_all_with_rand_reset.67297129573447176470876841852231407000524713573870102854752843731867221783959
Line 986, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 283978797 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 284298797 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 284398797 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 285538797 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 285618797 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1