OTP_CTRL Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.960s	816.154us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.460s	365.119us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.950s	711.334us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.450s	242.240us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.400s	323.789us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.420s	209.319us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.950s	711.334us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	323.789us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.900s	517.490us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	130.664us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	27.960s	3.224ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.450s	2.105ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	34.910s	16.461ms	10	10	100.00
		otp_ctrl_check_fail	1.475m	40.276ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.600s	4.290ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.300m	27.700ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.870s	11.357ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.333m	24.920ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.562m	20.500ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.004m	5.627ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.005m	174.160ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.100s	576.271us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.290s	225.767us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.640s	2.583ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.640s	2.583ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.460s	365.119us	5	5	100.00
		otp_ctrl_csr_rw	1.950s	711.334us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	323.789us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.560s	247.946us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.460s	365.119us	5	5	100.00
		otp_ctrl_csr_rw	1.950s	711.334us	20	20	100.00
		otp_ctrl_csr_aliasing	6.400s	323.789us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.560s	247.946us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.050s	20.240ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.050s	20.240ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_macro_errs	1.562m	20.500ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_macro_errs	1.562m	20.500ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.970s	20.507ms	200	200	100.00
		otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.450s	2.105ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.475m	40.276ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	58.730s	27.758ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.965m	24.243ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.600s	4.290ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.590s	7.702ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.562m	20.500ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.220s	7.554ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.203h	413.745ms	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.02	93.94	96.35	95.79	92.36	97.10	96.33	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 10 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 10 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.10954939998771477165686781193632189424981123282766192388072139722698191205896
      Line 8763, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25116671965 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (273561097 [0x104e3609] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 25116671965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.otp_ctrl_stress_all_with_rand_reset.21408170317875306829698685105671702770525534395390170993488663488958132461428
      Line 49268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34387371093 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3183199810 [0xbdbbc642] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 34387371093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

    • 21.otp_ctrl_stress_all_with_rand_reset.110270167839656643261059726219902890187109287666020114723076965566984673345616
      Line 25549, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 634677253212 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 634677253212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.otp_ctrl_stress_all_with_rand_reset.59025737789407838323935765884113873887015563334296523275968492904737546837744
      Line 19586, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107288367870 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 107288367870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.otp_ctrl_stress_all_with_rand_reset.39313727374849014739286084906289051363946115514421265339384303187581140529904
      Line 38727, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40078996329 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 40078996329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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