OTP_CTRL Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.360s	766.118us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.870s	1.054ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.840s	116.347us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	16.160s	6.790ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.550s	1.737ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.610s	1.690ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.840s	116.347us	20	20	100.00
		otp_ctrl_csr_aliasing	6.550s	1.737ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	49.957us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.560s	550.156us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.560s	326.398us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.570s	3.127ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	40.210s	2.475ms	10	10	100.00
		otp_ctrl_check_fail	52.710s	23.645ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.360s	3.891ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	44.010s	2.352ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.850s	12.990ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.510s	23.895ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.065m	20.750ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.795m	23.481ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.071m	115.758ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	532.589us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.910s	781.803us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.450s	631.586us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.450s	631.586us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.870s	1.054ms	5	5	100.00
		otp_ctrl_csr_rw	1.840s	116.347us	20	20	100.00
		otp_ctrl_csr_aliasing	6.550s	1.737ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.270s	2.155ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.870s	1.054ms	5	5	100.00
		otp_ctrl_csr_rw	1.840s	116.347us	20	20	100.00
		otp_ctrl_csr_aliasing	6.550s	1.737ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.270s	2.155ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
		otp_ctrl_tl_intg_err	32.710s	19.051ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	32.710s	19.051ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_macro_errs	1.065m	20.750ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_macro_errs	1.065m	20.750ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.040s	13.763ms	200	200	100.00
		otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.570s	3.127ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	52.710s	23.645ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	48.960s	8.900ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.023m	165.223ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.360s	3.891ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.490s	1.064ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.065m	20.750ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.670s	6.038ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.381h	339.411ms	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.00	93.89	96.75	96.12	91.41	97.19	96.33	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 10 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.8168448144688754364240269245082853031153755311471946790218497996208728325796
      Line 1850, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 432215490 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 432215490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.otp_ctrl_stress_all_with_rand_reset.93480901956202821354239428694370711019785504968419653907239103943086443322074
      Line 42464, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 218692033896 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 218692033896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.otp_ctrl_stress_all_with_rand_reset.55769970451205919001496248304199984149974945112080257991727140632310697278401
      Line 334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  41582515 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4132328219 [0xf64e531b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @  41582515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 59.otp_ctrl_stress_all_with_rand_reset.88925584044035105192302490001650623401282897495298422282645690017593699607569
      Line 38370, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 94891117902 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (117488826 [0x700bcba] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 94891117902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 38.otp_ctrl_stress_all_with_rand_reset.52805086822903470554736875686303002072105735408043169630146583744356733419993
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  26488063 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  26488063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 39.otp_ctrl_stress_all_with_rand_reset.45635219841506756961089980992305261940002538658582055892752030494653418928164
      Line 9372, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 66000246562 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 66000246562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.otp_ctrl_stress_all_with_rand_reset.89092814132218133032611755357408789387036750953540064541113877632479461978547
      Line 30744, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 124190364643 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1492 [0x5d4]) dai addr 5d4 rdata0 readout mismatch
        UVM_INFO @ 124190364643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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