OTP_CTRL Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.750s	62.365us	1	1	100.00
V1	smoke	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.140s	1.447ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.360s	589.036us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.810s	5.578ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.020s	1.163ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.570s	227.974us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.360s	589.036us	20	20	100.00
		otp_ctrl_csr_aliasing	5.020s	1.163ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.390s	69.087us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.570s	555.148us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.820s	1.170ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.820s	2.969ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	37.960s	3.772ms	10	10	100.00
		otp_ctrl_check_fail	1.831m	13.062ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.610s	3.774ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	41.230s	861.015us	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.120s	12.911ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.252m	21.388ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.451m	29.636ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	42.950s	15.590ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.291m	79.068ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.180s	565.810us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.120s	1.076ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.310s	2.752ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.310s	2.752ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.140s	1.447ms	5	5	100.00
		otp_ctrl_csr_rw	2.360s	589.036us	20	20	100.00
		otp_ctrl_csr_aliasing	5.020s	1.163ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.830s	1.617ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.140s	1.447ms	5	5	100.00
		otp_ctrl_csr_rw	2.360s	589.036us	20	20	100.00
		otp_ctrl_csr_aliasing	5.020s	1.163ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.830s	1.617ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
		otp_ctrl_tl_intg_err	32.650s	20.181ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	32.650s	20.181ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_macro_errs	1.451m	29.636ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_macro_errs	1.451m	29.636ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.520s	11.028ms	200	200	100.00
		otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.820s	2.969ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.831m	13.062ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.652m	19.777ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.162m	173.113ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.610s	3.774ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	23.090s	2.474ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.451m	29.636ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.990s	7.520ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.034h	1.653s	86	100	86.00
V3		TOTAL			87	101	86.14
		TOTAL			1329	1343	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.91	93.85	96.35	95.32	92.36	96.81	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.68167023904357473979360042995599697279959036080593445165532765848559335747628
      Line 18531, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 294736042809 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (361926858 [0x159290ca] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 294736042809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.37754705081269365964249177298493574442334264953623873986502594731920984048660
      Line 58724, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 81740205227 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (294364521 [0x118ba569] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 81740205227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 43.otp_ctrl_stress_all_with_rand_reset.99712020614150112028082786519496189261116642883695782725798510198580521748302
      Line 68234, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89206351953 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 89206351953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 63.otp_ctrl_stress_all_with_rand_reset.44426136027119906593054346378464094250861870063784967759455199696323475727766
      Line 67646, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 311349883633 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 311349883633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:205) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 11.otp_ctrl_stress_all_with_rand_reset.56054602693149965211313735036632814165015295310275214364975836162042374132031
      Line 14092, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 362927261 ps: (otp_ctrl_scoreboard.sv:205) [uvm_test_top.env.scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 362927261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 52.otp_ctrl_stress_all_with_rand_reset.27219263307064906319803894828461973051201814498897802444096708014988792905762
      Line 29011, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 25149779510 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 25149779510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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