OTP_CTRL Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.800s	58.481us	1	1	100.00
V1	smoke	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.910s	1.567ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.370s	641.668us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.990s	1.484ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.080s	840.813us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.690s	1.686ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.370s	641.668us	20	20	100.00
		otp_ctrl_csr_aliasing	4.080s	840.813us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.710s	521.190us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.400s	83.840us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.710s	693.620us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.350s	3.140ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	48.230s	17.437ms	10	10	100.00
		otp_ctrl_check_fail	53.520s	4.423ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.950s	4.680ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.550s	2.335ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.580s	12.054ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.125m	24.115ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.215m	33.147ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	3.937m	29.591ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.458m	37.956ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.070s	564.837us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.520s	247.651us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.360s	239.843us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.360s	239.843us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.910s	1.567ms	5	5	100.00
		otp_ctrl_csr_rw	2.370s	641.668us	20	20	100.00
		otp_ctrl_csr_aliasing	4.080s	840.813us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.910s	1.639ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.910s	1.567ms	5	5	100.00
		otp_ctrl_csr_rw	2.370s	641.668us	20	20	100.00
		otp_ctrl_csr_aliasing	4.080s	840.813us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.910s	1.639ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.030s	19.001ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.030s	19.001ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_macro_errs	1.215m	33.147ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_macro_errs	1.215m	33.147ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.099m	19.543ms	200	200	100.00
		otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.350s	3.140ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.520s	4.423ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.066m	24.811ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.694m	37.220ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.950s	4.680ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	21.040s	1.826ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.215m	33.147ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.880s	7.998ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.432h	2.187s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.97	93.85	96.65	95.79	91.89	97.14	96.19	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 5.otp_ctrl_stress_all_with_rand_reset.90353864567255850348287051468489919012679745842394968659964758387576188433699
      Line 32620, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67574652804 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1033900645 [0x3da01265] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 67574652804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.otp_ctrl_stress_all_with_rand_reset.87496064038052775366344565460703512522943081710499008329451173521547248770406
      Line 4854, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27305054873 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2650536954 [0x9dfbfbfa] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 27305054873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.109617874191671737339666582816609281228416694160224815444474062035705311622067
      Line 53233, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32875340529 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 32875340529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.otp_ctrl_stress_all_with_rand_reset.64473647450769181305539763050495901103023579033914131710925180511669671070882
      Line 39810, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 138340616266 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 138340616266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 3 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 38.otp_ctrl_stress_all_with_rand_reset.15798743608870797134391613061789512940444543546040486080518999134905458637599
      Line 37335, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 183442126842 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 183442126842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 50.otp_ctrl_stress_all_with_rand_reset.78474188435843390560915087042975106064605104682520307164247705132287204824214
      Line 21962, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 477877423592 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 477877423592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

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