OTP_CTRL Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.660s	795.423us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	393.917us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.390s	681.485us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.960s	6.936ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	10.280s	3.068ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.530s	153.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.390s	681.485us	20	20	100.00
		otp_ctrl_csr_aliasing	10.280s	3.068ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	132.902us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	45.604us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.520s	616.189us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.000s	2.389ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	45.530s	3.268ms	10	10	100.00
		otp_ctrl_check_fail	1.166m	5.534ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.660s	5.271ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	55.840s	22.322ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.710s	11.401ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	46.540s	2.801ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.180m	7.118ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.024m	22.514ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.982m	50.230ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.090s	581.417us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.460s	242.099us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.840s	3.057ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.840s	3.057ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	393.917us	5	5	100.00
		otp_ctrl_csr_rw	2.390s	681.485us	20	20	100.00
		otp_ctrl_csr_aliasing	10.280s	3.068ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.640s	124.167us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	393.917us	5	5	100.00
		otp_ctrl_csr_rw	2.390s	681.485us	20	20	100.00
		otp_ctrl_csr_aliasing	10.280s	3.068ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.640s	124.167us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
		otp_ctrl_tl_intg_err	46.390s	19.881ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	46.390s	19.881ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_macro_errs	1.180m	7.118ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_macro_errs	1.180m	7.118ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.430s	17.969ms	200	200	100.00
		otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.000s	2.389ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.166m	5.534ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	47.690s	3.333ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.595m	22.068ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.660s	5.271ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.740s	3.815ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.180m	7.118ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.120s	7.539ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.494h	898.388ms	88	100	88.00
V3		TOTAL			89	101	88.12
		TOTAL			1331	1343	99.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.02	93.91	96.43	95.91	92.12	97.10	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.77866495730417815053520923388502625114148666648176573026586291617503565981591
    Line 22963, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 263563862821 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 263563862821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.27934026227105666090430274026498109243270681171629944594173876788978970671805
    Line 6294, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10683997252 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 10683997252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.112101484188151995044741632390985938811410951338090315539276082144130417996568
    Line 3501, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 320469476 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (463768278 [0x1ba48ad6] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 320469476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.otp_ctrl_stress_all_with_rand_reset.20861391210225436403570434163003243336900939405363467829159731408860654683927
    Line 26925, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1080384970632 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2880820354 [0xabb5d482] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1080384970632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.53622657709591632665121877990480162150953549661430371100215814369362092504891
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27221795 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27221795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 37.otp_ctrl_stress_all_with_rand_reset.20050442230929758101376466343021155710238746287286260233715692396479931219228
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  79878599 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  79878599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

25.otp_ctrl_stress_all_with_rand_reset.71169010939097730978020270205854356246800859672369260692836318736125449139408
Line 44059, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 146556479188 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 146559645861 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 146559979195 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 146563812536 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 146563979203 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

61.otp_ctrl_stress_all_with_rand_reset.40129512065986658427240910397931094387351592929826630164967446031260035789998
Line 73717, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 411186664798 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 411186831465 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 411192331476 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 411193664812 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 411197498153 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1