OTP_CTRL Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	104.446us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.580s	137.819us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.480s	609.878us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.150s	1.612ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.160s	318.853us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.150s	1.765ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.480s	609.878us	20	20	100.00
		otp_ctrl_csr_aliasing	6.160s	318.853us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.410s	70.274us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.950s	532.529us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.090s	2.381ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.040s	3.088ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	54.240s	25.736ms	10	10	100.00
		otp_ctrl_check_fail	57.130s	21.715ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.500s	4.698ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.960s	2.908ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.580s	9.429ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2	otp_dai_errors	otp_ctrl_dai_errs	52.420s	25.796ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.116m	4.084ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	48.870s	11.937ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.292m	124.896ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.930s	553.363us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.700s	278.781us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.360s	645.665us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.360s	645.665us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.580s	137.819us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	609.878us	20	20	100.00
		otp_ctrl_csr_aliasing	6.160s	318.853us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	510.786us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.580s	137.819us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	609.878us	20	20	100.00
		otp_ctrl_csr_aliasing	6.160s	318.853us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	510.786us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.490s	10.357ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.490s	10.357ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_macro_errs	1.116m	4.084ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_macro_errs	1.116m	4.084ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.680s	11.432ms	199	200	99.50
		otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.040s	3.088ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	57.130s	21.715ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	42.930s	2.024ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.582m	41.441ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.500s	4.698ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.350s	638.948us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.116m	4.084ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.580s	3.021ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	59.131m	191.867ms	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.87	93.83	96.38	95.62	91.65	97.00	96.33	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 35.otp_ctrl_stress_all_with_rand_reset.72145813585033917012093290883647053974722497086619561650670555451440432702105
      Line 47727, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 772115145458 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 772115145458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.otp_ctrl_stress_all_with_rand_reset.98516913950533997714739778743036309954637122464609332990901770202956476766623
      Line 14654, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8992021913 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 8992021913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 7.otp_ctrl_stress_all_with_rand_reset.30735580398868715895101948581630539293052230515335749611341143557025873278547
      Line 122813, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 286608368056 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1848687149 [0x6e30ba2d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 286608368056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.otp_ctrl_stress_all_with_rand_reset.6066734551754224373033807872835362668437597419647533027534063700582861669849
      Line 26210, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 546793584706 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (374136932 [0x164ce064] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 546793584706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 15.otp_ctrl_stress_all_with_rand_reset.7401121977573523315260259319347963201837478581283283590373453813244927716316
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  52500259 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  52500259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 30.otp_ctrl_stress_all_with_rand_reset.71663696095834350704818581304605917591160332920091848493249594316884395136152
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 429807684 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 429807684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 11.otp_ctrl_stress_all_with_rand_reset.39266867901780768712529194234339772384047667578188897891588465981953740932426
      Line 3291, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 453735595 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
        UVM_INFO @ 453735595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *fc rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.otp_ctrl_stress_all_with_rand_reset.40511627391272688662105451829513057888570708734039989186735324761180274607858
      Line 273, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10898437084 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 425261109 [0x1958f835]) dai addr 6fc rdata0 readout mismatch
        UVM_INFO @ 10898437084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 88.otp_ctrl_stress_all_with_rand_reset.83001714644313697180762539946948811969668271383802158602380998803379346789760
      Line 23190, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 101681405429 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 101681405429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:

  • Test otp_ctrl_parallel_lc_esc has 1 failures.

    • 95.otp_ctrl_parallel_lc_esc.7094945126010985940022884472513188340820135054810598950130610586281125486777
      Line 2452, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest/run.log

        UVM_ERROR @ 109590385 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
        UVM_INFO @ 109590385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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