OTP_CTRL Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	125.290us	1	1	100.00
V1	smoke	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.440s	1.053ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.930s	65.611us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.760s	6.714ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.860s	192.707us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.260s	1.561ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.930s	65.611us	20	20	100.00
		otp_ctrl_csr_aliasing	5.860s	192.707us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.530s	527.231us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.850s	527.658us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.500s	9.897ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.020s	3.080ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	36.270s	7.545ms	10	10	100.00
		otp_ctrl_check_fail	1.092m	6.378ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.020s	4.301ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.672m	5.214ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.250s	3.205ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	51.890s	24.446ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	59.080s	5.027ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.998m	11.518ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.712m	68.807ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.150s	588.745us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.850s	570.724us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.370s	2.676ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.370s	2.676ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.440s	1.053ms	5	5	100.00
		otp_ctrl_csr_rw	1.930s	65.611us	20	20	100.00
		otp_ctrl_csr_aliasing	5.860s	192.707us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.450s	1.535ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.440s	1.053ms	5	5	100.00
		otp_ctrl_csr_rw	1.930s	65.611us	20	20	100.00
		otp_ctrl_csr_aliasing	5.860s	192.707us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.450s	1.535ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.730s	19.063ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.730s	19.063ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_macro_errs	59.080s	5.027ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_macro_errs	59.080s	5.027ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.410s	11.574ms	200	200	100.00
		otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.020s	3.080ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.092m	6.378ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	3.082m	23.408ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.031m	154.535ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.020s	4.301ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	21.240s	8.932ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	59.080s	5.027ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.630s	7.940ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.111h	2.402s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.91	96.35	95.59	91.89	97.09	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.16238234918898204809032538781029841640988984408269007517095312059966916943746
    Line 10784, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5635816186 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 5635816186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.otp_ctrl_stress_all_with_rand_reset.32831466454280325059214977853613940789546177153850704338618480742804495603164
    Line 1529, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9010423275 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 9010423275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.57502372877087509695416295486125504843888667747993150572936961532036384250666
    Line 42300, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26835325559 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2260778525 [0x86c0be1d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 26835325559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.3184269360927375683929558985828965133478124260488572315204916877811375727612
    Line 31401, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133474069054 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1905585313 [0x7194eca1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 133474069054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

7.otp_ctrl_stress_all_with_rand_reset.24956036565058224413798581564260110788379952785489198002695020795991650462780
Line 21081, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 161512461367 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 161512628034 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 161515961374 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 161516461375 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 161519961382 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

82.otp_ctrl_stress_all_with_rand_reset.44692663368454734900439126149695515792148659781280969002885262264239027757973
Line 1845, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 781326551 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 781868222 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 781909889 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 783118232 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 783159899 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.otp_ctrl_stress_all_with_rand_reset.5786838230112988615073152130166303040054781710804427922924819513469674950544
    Line 4976, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39114704113 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1060 [0x424]) dai addr 424 rdata0 readout mismatch
  UVM_INFO @ 39114704113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 69.otp_ctrl_stress_all_with_rand_reset.103663888161542623267828174264141567217098789144424577897587675066975294002042
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27839760 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27839760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr c* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.93281918120976188984320192172516046522758561878461648025284418602144242115486
    Line 40816, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11217281967 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 196 [0xc4]) dai addr c4 rdata0 readout mismatch
  UVM_INFO @ 11217281967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```