OTP_CTRL Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.940s	772.693us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.460s	125.193us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.290s	656.312us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.450s	4.149ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.680s	3.265ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.560s	1.593ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.290s	656.312us	20	20	100.00
		otp_ctrl_csr_aliasing	7.680s	3.265ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.050s	555.595us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.500s	37.620us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.840s	1.231ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.830s	2.629ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	22.960s	2.389ms	10	10	100.00
		otp_ctrl_check_fail	44.990s	16.528ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.600s	4.405ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.175m	3.849ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.430s	12.766ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.050s	22.742ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.689m	20.262ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.092m	11.351ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.261m	26.634ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.020s	564.202us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.150s	986.068us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.100s	238.572us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.100s	238.572us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.460s	125.193us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	656.312us	20	20	100.00
		otp_ctrl_csr_aliasing	7.680s	3.265ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.920s	2.103ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.460s	125.193us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	656.312us	20	20	100.00
		otp_ctrl_csr_aliasing	7.680s	3.265ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.920s	2.103ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.530s	3.734ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.530s	3.734ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_macro_errs	2.689m	20.262ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_macro_errs	2.689m	20.262ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.640s	19.080ms	200	200	100.00
		otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.830s	2.629ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	44.990s	16.528ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	54.190s	25.949ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.880m	154.694ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.600s	4.405ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.510s	7.181ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.689m	20.262ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.710s	3.394ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.583h	1.905s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.79	93.89	96.32	95.58	90.93	97.09	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 11 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 11 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.113828898263781362656499132208407668481225168584961923215227485106121269046659
    Line 23265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4886877752 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 4886877752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.otp_ctrl_stress_all_with_rand_reset.58410322656654367870644683653576340659453591765638780390680509477304424424223
    Line 30499, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3375595858 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 3375595858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.100018477717567798659437779364903513792827679058576896514027189458994793551075
    Line 15299, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1552856596 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3122083484 [0xba17369c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1552856596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.otp_ctrl_stress_all_with_rand_reset.47396707931179786546368775171725672892711085523324193648084919702771251286684
    Line 20133, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33393810893 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3306219445 [0xc510e7b5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 33393810893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

47.otp_ctrl_stress_all_with_rand_reset.94815478581601238489760532214885766900707953456013994380710789922418583257201
Line 7236, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 15208604590 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 15209278054 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15209298462 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15210135190 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15210380086 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

61.otp_ctrl_stress_all_with_rand_reset.46030224585254359203938264593165434096848851638302438690547220260778755993063
Line 6894, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 17475931677 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 17475971677 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 17476671677 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 17476691677 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 17477671677 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.25836094173188026067325189796250384579395437389824455189461294435261365839861
    Line 65408, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15859405464 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 15859405464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 79.otp_ctrl_stress_all_with_rand_reset.9162670408121702282132538226629014954614806370558858114312099700552542293881
    Line 274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13387344897 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 388828419 [0x172d0d03]) dai addr 770 rdata0 readout mismatch
  UVM_INFO @ 13387344897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```