OTP_CTRL Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.580s	51.741us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.890s	138.218us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.880s	704.667us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.820s	550.672us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.260s	3.080ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.450s	108.349us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.880s	704.667us	20	20	100.00
		otp_ctrl_csr_aliasing	9.260s	3.080ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.780s	68.530us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.620s	35.898us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	15.990s	1.195ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	15.200s	3.305ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.640s	16.878ms	10	10	100.00
		otp_ctrl_check_fail	53.120s	17.568ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.690s	4.503ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.680s	25.732ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.210s	11.787ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	58.970s	17.051ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	55.410s	26.570ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.038m	6.477ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.082m	60.651ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.150s	552.349us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.920s	737.972us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.750s	625.437us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.750s	625.437us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.890s	138.218us	5	5	100.00
		otp_ctrl_csr_rw	2.880s	704.667us	20	20	100.00
		otp_ctrl_csr_aliasing	9.260s	3.080ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	170.881us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.890s	138.218us	5	5	100.00
		otp_ctrl_csr_rw	2.880s	704.667us	20	20	100.00
		otp_ctrl_csr_aliasing	9.260s	3.080ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	170.881us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.780s	20.151ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.780s	20.151ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_macro_errs	55.410s	26.570ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_macro_errs	55.410s	26.570ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.410s	16.559ms	200	200	100.00
		otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	15.200s	3.305ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.120s	17.568ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.005m	33.260ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	7.362m	165.391ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.690s	4.503ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.420s	1.658ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	55.410s	26.570ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.830s	7.519ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	5.422m	73.831ms	46	100	46.00
V3		TOTAL			47	101	46.53
		TOTAL			1288	1343	95.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.10	93.68	96.65	96.02	92.29	97.50	96.37	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 27 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 27 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.27342173711986633103291711752666340027967204321613067896574750106245834581264
    Line 7745, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 905769603 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 905769603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otp_ctrl_stress_all_with_rand_reset.43079315451876927500086502806402471848394117754993345262615191242731152301587
    Line 3538, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1990061654 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1990061654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 14 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 14 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.44643602519330311134862302479875418310399715123568505965072102085595239236781
    Line 25040, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4976272228 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1069523243 [0x3fbfa12b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 4976272228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.otp_ctrl_stress_all_with_rand_reset.45635786036977303434544127900695454020093701438054815604427368847242055898745
    Line 565, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 354392373 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3682717447 [0xdb81cf07] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 354392373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.10595587000244159387499411223881351177101681666385109646620681494360908826860
    Line 7749, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1102143979 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 1102143979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_stress_all_with_rand_reset.40734510615463327332767669592209495411594009425350331231772233765790298609791
    Line 653, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102180916 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 102180916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.75301202610162554187795882084315286907795120487654297199383376682345290102218
    Line 82, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  52636404 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  52636404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 98.otp_ctrl_stress_all_with_rand_reset.44340798187098471454853814959794714802568240973769516967996147043250943000177
    Line 10798, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 10179329466 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 10179329466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.otp_ctrl_csr_mem_rw_with_rand_reset.110238365132917637519819135446950379040986715146355985738076613800670770894306
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 120345344 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 120345344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

25.otp_ctrl_stress_all_with_rand_reset.97628809455953962925707901735999699950318529849061452503151947697939671971198
Line 2931, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2668748123 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2670956474 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2670998141 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2671956482 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2671998149 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

55.otp_ctrl_stress_all_with_rand_reset.15254768733139792956662204743565976046491736032757871565931347605591574616842
Line 1531, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1663537947 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 1663787949 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1664121285 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1664996292 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1665246294 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 74.otp_ctrl_stress_all_with_rand_reset.20898999525224254401405719817525714368395536557767095219158718278411983504545
    Line 6211, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2473257032 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 64 [0x40]) dai addr 40 rdata0 readout mismatch
  UVM_INFO @ 2473257032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 95.otp_ctrl_stress_all_with_rand_reset.57523157859566714270414464106368854230636468051306997124322799354163915889507
    Line 43896, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8923353755 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1332 [0x534]) dai addr 534 rdata0 readout mismatch
  UVM_INFO @ 8923353755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 85.otp_ctrl_stress_all_with_rand_reset.109419265903362734153456857378144918791774376922759072350746891878060027971216
    Line 10113, in log /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17096969677 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1580 [0x62c]) dai addr 62c rdata0 readout mismatch
  UVM_INFO @ 17096969677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```