OTP_CTRL Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.480s	110.647us	1	1	100.00
V1	smoke	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.710s	1.555ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.470s	632.716us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.670s	831.746us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.180s	163.291us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.090s	1.671ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.470s	632.716us	20	20	100.00
		otp_ctrl_csr_aliasing	5.180s	163.291us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.290s	64.058us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.640s	535.261us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	25.580s	709.425us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.500s	2.685ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	46.860s	12.838ms	10	10	100.00
		otp_ctrl_check_fail	1.539m	10.746ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.980s	4.221ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.123m	5.435ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.370s	3.051ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.045m	21.838ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.199m	6.818ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.687m	17.530ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.143m	41.275ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.960s	567.366us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.790s	306.906us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.820s	2.614ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.820s	2.614ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.710s	1.555ms	5	5	100.00
		otp_ctrl_csr_rw	2.470s	632.716us	20	20	100.00
		otp_ctrl_csr_aliasing	5.180s	163.291us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.520s	1.902ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.710s	1.555ms	5	5	100.00
		otp_ctrl_csr_rw	2.470s	632.716us	20	20	100.00
		otp_ctrl_csr_aliasing	5.180s	163.291us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.520s	1.902ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.260s	20.231ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.260s	20.231ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_macro_errs	1.199m	6.818ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_macro_errs	1.199m	6.818ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.030s	14.290ms	200	200	100.00
		otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.500s	2.685ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.539m	10.746ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	4.017m	27.578ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.189m	173.018ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.980s	4.221ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	37.850s	7.433ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.199m	6.818ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.000s	3.073ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.610m	15.488ms	63	100	63.00
V3		TOTAL			64	101	63.37
		TOTAL			1306	1343	97.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.18	93.73	96.75	95.89	92.77	97.54	96.37	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 19 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 19 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.43982037974634439139422244432065652181698365078824547793475852772471661413210
    Line 17525, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57069535453 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 57069535453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.20898526887213772612421312855351936692502298960925238313038143010206913307776
    Line 37748, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5475448070 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 5475448070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.45062351712037466795817006412393612084213554615904613127584292392395188593702
    Line 4663, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11715310792 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (186256885 [0xb1a0df5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 11715310792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.otp_ctrl_stress_all_with_rand_reset.58311224018442835909326459337964758776196311276938930274375970081258226439492
    Line 10186, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23430259024 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2299224741 [0x890b62a5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 23430259024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.84706666804679426813458108241445253818263821313805911123126096565034914012900
    Line 799, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13128493324 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1536 [0x600]) dai addr 600 rdata0 readout mismatch
  UVM_INFO @ 13128493324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 77.otp_ctrl_stress_all_with_rand_reset.85126582168259832448367205095401040805880910908244751438885634635028577435692
    Line 18031, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17429887349 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1126335426 [0x432283c2]) dai addr 730 rdata0 readout mismatch
  UVM_INFO @ 17429887349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=310) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.29622148692605396603264651001668760304637938700782626983232742144722050248139
    Line 66967, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16147285796 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xad26d010, Comparison=CompareOpEq, exp_data=0x0, call_count=310)
  UVM_INFO @ 16147285796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.1390969811440260775747400337316650506803043120408356520986823335816689542722
    Line 10331, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26919353563 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26919353563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 51.otp_ctrl_stress_all_with_rand_reset.74525793072025062151300012558629577685040968992221539813337893381343220160651
    Line 3683, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1877718160 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 1877718160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 67.otp_ctrl_stress_all_with_rand_reset.45201114043198945935816087428307934278837200078124188742836095039417108815384
    Line 239, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 224943357 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 224943357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

70.otp_ctrl_stress_all_with_rand_reset.79281495933678481604062812727845239680387163795175129561794761727062968423567
Line 17878, in log /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 3997291963 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 3997551963 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3997561963 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3998221963 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 3998231963 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1