OTP_CTRL Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.500s	188.571us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.800s	1.532ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.610s	684.241us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.180s	563.952us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.580s	3.007ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.020s	1.651ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.610s	684.241us	20	20	100.00
		otp_ctrl_csr_aliasing	9.580s	3.007ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.690s	498.328us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.650s	74.658us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.140s	1.565ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.170s	2.682ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	26.450s	1.234ms	10	10	100.00
		otp_ctrl_check_fail	41.540s	3.780ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.320s	1.268ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.200s	11.749ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.840s	12.296ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.178m	26.300ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.012m	9.371ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	4.120m	49.364ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.116m	99.837ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	525.397us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.500s	244.245us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.680s	2.891ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.680s	2.891ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.800s	1.532ms	5	5	100.00
		otp_ctrl_csr_rw	2.610s	684.241us	20	20	100.00
		otp_ctrl_csr_aliasing	9.580s	3.007ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.610s	2.202ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.800s	1.532ms	5	5	100.00
		otp_ctrl_csr_rw	2.610s	684.241us	20	20	100.00
		otp_ctrl_csr_aliasing	9.580s	3.007ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.610s	2.202ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.580s	18.827ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.580s	18.827ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_macro_errs	1.012m	9.371ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_macro_errs	1.012m	9.371ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	30.300s	4.632ms	200	200	100.00
		otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.170s	2.682ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	41.540s	3.780ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.730m	10.298ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.122m	173.293ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.320s	1.268ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.760s	8.874ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.012m	9.371ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.570s	7.518ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.216m	85.452ms	53	100	53.00
V3		TOTAL			54	101	53.47
		TOTAL			1296	1343	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.12	93.73	96.73	95.73	92.53	97.54	96.37	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 23 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 23 failures.

    • 2.otp_ctrl_stress_all_with_rand_reset.41670768138123979651130929032348428517652342819769107992703270263223708453667
      Line 4308, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 201559526 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 201559526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.otp_ctrl_stress_all_with_rand_reset.104074268529374733748987251149298637390360274623240086392486842360656379187308
      Line 12811, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1924873112 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1924873112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 16 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 16 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.1668017186475391033949398178484760187087944195802398983055115775832030120981
      Line 24290, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1425481475 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2038553281 [0x7981dac1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1425481475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.otp_ctrl_stress_all_with_rand_reset.97602596178765163009788860361176597609694867652177609491312972068881554635889
      Line 2760, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15223992492 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (130242046 [0x7c355fe] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 15223992492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 56.otp_ctrl_stress_all_with_rand_reset.93239563849942698211336209871381946773949008319534947036837242656753417710144
      Line 153, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 141180050 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 141180050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 61.otp_ctrl_stress_all_with_rand_reset.89806603152415290845550216194794811364412462985112254909620553635489686928823
      Line 7230, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1285330103 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 1285330103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 31.otp_ctrl_stress_all_with_rand_reset.52473172874391855414007344363870787838429901277076982394456459697207856155793
      Line 15522, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21959309281 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21959309281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 67.otp_ctrl_stress_all_with_rand_reset.107719618843770558914046994844398370598995306678323269591571795805495559789171
      Line 13910, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14798923171 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14798923171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.88860032813755081711817812575401434902066291012126332120980031421140190160754
      Line 7148, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10306245975 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1236 [0x4d4]) dai addr 4d4 rdata0 readout mismatch
        UVM_INFO @ 10306245975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.otp_ctrl_stress_all_with_rand_reset.24674766006427571972037929375499096535072550275896064921414904640186294138935
      Line 1081, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16756934847 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 367225146 [0x15e3693a]) dai addr 730 rdata0 readout mismatch
        UVM_INFO @ 16756934847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 95.otp_ctrl_stress_all_with_rand_reset.32043617711151962479122729856402433298903229814029226209851223967790515597308
      Line 7525, in log /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11308292424 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
        UVM_INFO @ 11308292424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.10_10.15.56
• 2024.10.04_00.42.49
• 2024.09.25_11.01.49
• 2024.09.19_09.05.36
• 2024.09.12_10.17.11
• 2024.09.10_08.12.02